System Level Architecture Exploration for Reconfigurable Systems on Chip

Konstantinos Masselos; Yang Qu; Kari Tiensyrjä; Nikolaos S. Voros; Miroslav Cupak; Luc Rijnders; Marko Pettissalo

doi:10.1109/FPL.2006.311195

System Level Architecture Exploration for Reconfigurable Systems on Chip

Konstantinos Masselos
, Yang Qu
, Kari Tiensyrjä
, Nikolaos S. Voros
, Miroslav Cupak
, Luc Rijnders
, Marko Pettissalo

VTT Technical Research Centre of Finland

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

During the last years, a new type of Systems-on-Chip called, Reconfigurable Systems-on-Chip (RSoCs), has appeared. The design of such systems is a complex task and requires innovative methods to support the development process. In this paper, we present two alternative approaches for the efficient architecture exploration of RSoCs, based on SystemC language and on OCAPI-xl environment. The approaches introduced, allow early evaluation of alternative mappings of system's functionality onto different architectures. As a result, the time consuming iterations from lower design stages are eliminated, and reduced design time is achieved. The paper proves the effectiveness of the proposed approaches through three different case studies, borrowed from complementary domains.

Original language	English
Title of host publication	2006 International Conference on Field Programmable Logic and Applications
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	59-64
ISBN (Print)	1-4244-0312-X
DOIs	https://doi.org/10.1109/FPL.2006.311195
Publication status	Published - 2006
MoE publication type	A4 Article in a conference publication
Event	2006 International Conference on Field Programmable Logic and Applications - Madrid, Spain Duration: 28 Aug 2006 → 30 Aug 2006

Conference

Conference	2006 International Conference on Field Programmable Logic and Applications
Country/Territory	Spain
City	Madrid
Period	28/08/06 → 30/08/06

Access to Document

10.1109/FPL.2006.311195

Cite this

@inproceedings{5a1977fd932f4dbfafa7b2f003bd2de0,

title = "System Level Architecture Exploration for Reconfigurable Systems on Chip",

abstract = "During the last years, a new type of Systems-on-Chip called, Reconfigurable Systems-on-Chip (RSoCs), has appeared. The design of such systems is a complex task and requires innovative methods to support the development process. In this paper, we present two alternative approaches for the efficient architecture exploration of RSoCs, based on SystemC language and on OCAPI-xl environment. The approaches introduced, allow early evaluation of alternative mappings of system's functionality onto different architectures. As a result, the time consuming iterations from lower design stages are eliminated, and reduced design time is achieved. The paper proves the effectiveness of the proposed approaches through three different case studies, borrowed from complementary domains.",

author = "Konstantinos Masselos and Yang Qu and Kari Tiensyrj{\"a} and Voros, \{Nikolaos S.\} and Miroslav Cupak and Luc Rijnders and Marko Pettissalo",

year = "2006",

doi = "10.1109/FPL.2006.311195",

language = "English",

isbn = "1-4244-0312-X",

pages = "59--64",

booktitle = "2006 International Conference on Field Programmable Logic and Applications",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "2006 International Conference on Field Programmable Logic and Applications ; Conference date: 28-08-2006 Through 30-08-2006",

}

Masselos, K, Qu, Y, Tiensyrjä, K, Voros, NS, Cupak, M, Rijnders, L & Pettissalo, M 2006, System Level Architecture Exploration for Reconfigurable Systems on Chip. in 2006 International Conference on Field Programmable Logic and Applications. IEEE Institute of Electrical and Electronic Engineers, pp. 59-64, 2006 International Conference on Field Programmable Logic and Applications, Madrid, Spain, 28/08/06. https://doi.org/10.1109/FPL.2006.311195

System Level Architecture Exploration for Reconfigurable Systems on Chip. / Masselos, Konstantinos; Qu, Yang; Tiensyrjä, Kari et al.
2006 International Conference on Field Programmable Logic and Applications. IEEE Institute of Electrical and Electronic Engineers, 2006. p. 59-64.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - System Level Architecture Exploration for Reconfigurable Systems on Chip

AU - Masselos, Konstantinos

AU - Qu, Yang

AU - Tiensyrjä, Kari

AU - Voros, Nikolaos S.

AU - Cupak, Miroslav

AU - Rijnders, Luc

AU - Pettissalo, Marko

PY - 2006

Y1 - 2006

N2 - During the last years, a new type of Systems-on-Chip called, Reconfigurable Systems-on-Chip (RSoCs), has appeared. The design of such systems is a complex task and requires innovative methods to support the development process. In this paper, we present two alternative approaches for the efficient architecture exploration of RSoCs, based on SystemC language and on OCAPI-xl environment. The approaches introduced, allow early evaluation of alternative mappings of system's functionality onto different architectures. As a result, the time consuming iterations from lower design stages are eliminated, and reduced design time is achieved. The paper proves the effectiveness of the proposed approaches through three different case studies, borrowed from complementary domains.

AB - During the last years, a new type of Systems-on-Chip called, Reconfigurable Systems-on-Chip (RSoCs), has appeared. The design of such systems is a complex task and requires innovative methods to support the development process. In this paper, we present two alternative approaches for the efficient architecture exploration of RSoCs, based on SystemC language and on OCAPI-xl environment. The approaches introduced, allow early evaluation of alternative mappings of system's functionality onto different architectures. As a result, the time consuming iterations from lower design stages are eliminated, and reduced design time is achieved. The paper proves the effectiveness of the proposed approaches through three different case studies, borrowed from complementary domains.

U2 - 10.1109/FPL.2006.311195

DO - 10.1109/FPL.2006.311195

M3 - Conference article in proceedings

SN - 1-4244-0312-X

SP - 59

EP - 64

BT - 2006 International Conference on Field Programmable Logic and Applications

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 2006 International Conference on Field Programmable Logic and Applications

Y2 - 28 August 2006 through 30 August 2006

ER -

System Level Architecture Exploration for Reconfigurable Systems on Chip

Abstract

Conference

Access to Document

Fingerprint

Cite this