System-level design and configuration management for run-time reconfigurable devices: Dissertation

Yang Qu

Research output: ThesisDissertation

Abstract

Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also deliver high performance for computation-intensive tasks. Advanced features such as run-time reconfiguration (RTR) allow multiple tasks to be mapped onto the same device either simultaneously or multiplexed in time domain. This new type of computing element also brings new challenges in the design process. Design supports at the system level are needed. In addition, the configuration latency and the configuration energy involved in each reconfiguration process can largely degrade the system performance. Approaches to efficiently manage the configuration processes are needed in order to effectively reduce its negative impacts. In this thesis, system-level supports for design of DRHW and various configuration management approaches for reducing the impact of configuration overhead are presented. Our system-level design supports are based on the SystemC environment. An estimation technique for system partitioning and a DRHW modeling technique are developed. The main idea is to help designers in the early design phase to evaluate the benefit of moving some components from fixed hardware implementation to DRHW. The supports have been applied in a WCDMA case study. In order to efficiently apply the multi-tasking feature of DRHW, we have developed three static task scheduling techniques and a run-time scheduling technique. The static schedulers include a list-based heuristic approach, an optimal approach based on constraint programming and a guided random search approach using a genetic algorithm. They are evaluated using both random tasks and real applications. The run-time scheduling uses a novel configuration locking technique. The idea is to dynamically track the task status and lock the most frequently used tasks on DRHW in order to reduce the number of reconfigurations. In addition, we present two novel techniques to reduce the configuration overhead. The first is configuration parallelism. Its idea is to enable tasks to be loaded in parallel in order to better exploit their parallelism. The second is dynamic voltage scaling. The idea is to apply low supply voltage in reconfiguration process when possible in order to reduce the configuration energy.
Original languageEnglish
QualificationDoctor Degree
Awarding Institution
  • Tampere University of Technology (TUT)
Supervisors/Advisors
  • Nurmi, Jari, Supervisor, External person
Award date30 Nov 2007
Place of PublicationEspoo
Publisher
Print ISBNs978-951-38-7053-9
Electronic ISBNs978-951-38-7054-6
Publication statusPublished - 2007
MoE publication typeG4 Doctoral dissertation (monograph)

Fingerprint

Reconfigurable hardware
Scheduling
Multitasking
Reusability
Computer hardware
Genetic algorithms
Silicon
Electric potential

Keywords

  • dynamically reconfigurable hardware
  • run-time reconfiguration
  • system-level design
  • task scheduling
  • configuration locking
  • configuration parallelism

Cite this

Qu, Yang. / System-level design and configuration management for run-time reconfigurable devices : Dissertation. Espoo : VTT Technical Research Centre of Finland, 2007. 137 p.
@phdthesis{c5b9c2d6ed5f46f2865d48b241880a02,
title = "System-level design and configuration management for run-time reconfigurable devices: Dissertation",
abstract = "Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also deliver high performance for computation-intensive tasks. Advanced features such as run-time reconfiguration (RTR) allow multiple tasks to be mapped onto the same device either simultaneously or multiplexed in time domain. This new type of computing element also brings new challenges in the design process. Design supports at the system level are needed. In addition, the configuration latency and the configuration energy involved in each reconfiguration process can largely degrade the system performance. Approaches to efficiently manage the configuration processes are needed in order to effectively reduce its negative impacts. In this thesis, system-level supports for design of DRHW and various configuration management approaches for reducing the impact of configuration overhead are presented. Our system-level design supports are based on the SystemC environment. An estimation technique for system partitioning and a DRHW modeling technique are developed. The main idea is to help designers in the early design phase to evaluate the benefit of moving some components from fixed hardware implementation to DRHW. The supports have been applied in a WCDMA case study. In order to efficiently apply the multi-tasking feature of DRHW, we have developed three static task scheduling techniques and a run-time scheduling technique. The static schedulers include a list-based heuristic approach, an optimal approach based on constraint programming and a guided random search approach using a genetic algorithm. They are evaluated using both random tasks and real applications. The run-time scheduling uses a novel configuration locking technique. The idea is to dynamically track the task status and lock the most frequently used tasks on DRHW in order to reduce the number of reconfigurations. In addition, we present two novel techniques to reduce the configuration overhead. The first is configuration parallelism. Its idea is to enable tasks to be loaded in parallel in order to better exploit their parallelism. The second is dynamic voltage scaling. The idea is to apply low supply voltage in reconfiguration process when possible in order to reduce the configuration energy.",
keywords = "dynamically reconfigurable hardware, run-time reconfiguration, system-level design, task scheduling, configuration locking, configuration parallelism",
author = "Yang Qu",
note = "Project code: 6769",
year = "2007",
language = "English",
isbn = "978-951-38-7053-9",
series = "VTT Publications",
publisher = "VTT Technical Research Centre of Finland",
number = "659",
address = "Finland",
school = "Tampere University of Technology (TUT)",

}

Qu, Y 2007, 'System-level design and configuration management for run-time reconfigurable devices: Dissertation', Doctor Degree, Tampere University of Technology (TUT), Espoo.

System-level design and configuration management for run-time reconfigurable devices : Dissertation. / Qu, Yang.

Espoo : VTT Technical Research Centre of Finland, 2007. 137 p.

Research output: ThesisDissertation

TY - THES

T1 - System-level design and configuration management for run-time reconfigurable devices

T2 - Dissertation

AU - Qu, Yang

N1 - Project code: 6769

PY - 2007

Y1 - 2007

N2 - Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also deliver high performance for computation-intensive tasks. Advanced features such as run-time reconfiguration (RTR) allow multiple tasks to be mapped onto the same device either simultaneously or multiplexed in time domain. This new type of computing element also brings new challenges in the design process. Design supports at the system level are needed. In addition, the configuration latency and the configuration energy involved in each reconfiguration process can largely degrade the system performance. Approaches to efficiently manage the configuration processes are needed in order to effectively reduce its negative impacts. In this thesis, system-level supports for design of DRHW and various configuration management approaches for reducing the impact of configuration overhead are presented. Our system-level design supports are based on the SystemC environment. An estimation technique for system partitioning and a DRHW modeling technique are developed. The main idea is to help designers in the early design phase to evaluate the benefit of moving some components from fixed hardware implementation to DRHW. The supports have been applied in a WCDMA case study. In order to efficiently apply the multi-tasking feature of DRHW, we have developed three static task scheduling techniques and a run-time scheduling technique. The static schedulers include a list-based heuristic approach, an optimal approach based on constraint programming and a guided random search approach using a genetic algorithm. They are evaluated using both random tasks and real applications. The run-time scheduling uses a novel configuration locking technique. The idea is to dynamically track the task status and lock the most frequently used tasks on DRHW in order to reduce the number of reconfigurations. In addition, we present two novel techniques to reduce the configuration overhead. The first is configuration parallelism. Its idea is to enable tasks to be loaded in parallel in order to better exploit their parallelism. The second is dynamic voltage scaling. The idea is to apply low supply voltage in reconfiguration process when possible in order to reduce the configuration energy.

AB - Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also deliver high performance for computation-intensive tasks. Advanced features such as run-time reconfiguration (RTR) allow multiple tasks to be mapped onto the same device either simultaneously or multiplexed in time domain. This new type of computing element also brings new challenges in the design process. Design supports at the system level are needed. In addition, the configuration latency and the configuration energy involved in each reconfiguration process can largely degrade the system performance. Approaches to efficiently manage the configuration processes are needed in order to effectively reduce its negative impacts. In this thesis, system-level supports for design of DRHW and various configuration management approaches for reducing the impact of configuration overhead are presented. Our system-level design supports are based on the SystemC environment. An estimation technique for system partitioning and a DRHW modeling technique are developed. The main idea is to help designers in the early design phase to evaluate the benefit of moving some components from fixed hardware implementation to DRHW. The supports have been applied in a WCDMA case study. In order to efficiently apply the multi-tasking feature of DRHW, we have developed three static task scheduling techniques and a run-time scheduling technique. The static schedulers include a list-based heuristic approach, an optimal approach based on constraint programming and a guided random search approach using a genetic algorithm. They are evaluated using both random tasks and real applications. The run-time scheduling uses a novel configuration locking technique. The idea is to dynamically track the task status and lock the most frequently used tasks on DRHW in order to reduce the number of reconfigurations. In addition, we present two novel techniques to reduce the configuration overhead. The first is configuration parallelism. Its idea is to enable tasks to be loaded in parallel in order to better exploit their parallelism. The second is dynamic voltage scaling. The idea is to apply low supply voltage in reconfiguration process when possible in order to reduce the configuration energy.

KW - dynamically reconfigurable hardware

KW - run-time reconfiguration

KW - system-level design

KW - task scheduling

KW - configuration locking

KW - configuration parallelism

M3 - Dissertation

SN - 978-951-38-7053-9

T3 - VTT Publications

PB - VTT Technical Research Centre of Finland

CY - Espoo

ER -

Qu Y. System-level design and configuration management for run-time reconfigurable devices: Dissertation. Espoo: VTT Technical Research Centre of Finland, 2007. 137 p.