System-level design for partially reconfigurable hardware

Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

1 Citation (Scopus)


In this paper, we present a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.
Original languageEnglish
Title of host publicationProceedings
Subtitle of host publicationIEEE International Symposium on Circuits and Systems, ISCAS 2007
PublisherIEEE Institute of Electrical and Electronic Engineers
ISBN (Print)1-4244-0920-9, 1-4244-0921-7
Publication statusPublished - 2007
MoE publication typeA4 Article in a conference publication
EventIEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 27 May 200730 May 2007


ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2007
Abbreviated titleISCAS 2007
CountryUnited States
CityNew Orleans, LA


  • run-time reconfigurable hardware
  • SystemC
  • system-level design

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