System-level design for partially reconfigurable hardware

Yang Qu; Kari Tiensyrjä; Juha-Pekka Soininen; Jari Nurmi

doi:10.1109/ISCAS.2007.378619

System-level design for partially reconfigurable hardware

Yang Qu
, Kari Tiensyrjä
, Juha-Pekka Soininen
, Jari Nurmi

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

1 Citation (Scopus)

Abstract

In this paper, we present a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems, ISCAS 2007
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	2738-2741
ISBN (Electronic)	978-1-4244-0921-1
ISBN (Print)	978-1-4244-0920-4
DOIs	https://doi.org/10.1109/ISCAS.2007.378619
Publication status	Published - 2007
MoE publication type	A4 Article in a conference publication
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States Duration: 27 May 2007 → 30 May 2007

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2007
Abbreviated title	ISCAS 2007
Country/Territory	United States
City	New Orleans, LA
Period	27/05/07 → 30/05/07

Keywords

run-time reconfigurable hardware
SystemC
system-level design

Access to Document

10.1109/ISCAS.2007.378619

Cite this

@inproceedings{01385f0aba9846a9bd7c66246c1e24e9,

title = "System-level design for partially reconfigurable hardware",

abstract = "In this paper, we present a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.",

keywords = "run-time reconfigurable hardware, SystemC, system-level design",

author = "Yang Qu and Kari Tiensyrj{\"a} and Juha-Pekka Soininen and Jari Nurmi",

year = "2007",

doi = "10.1109/ISCAS.2007.378619",

language = "English",

isbn = "978-1-4244-0920-4",

pages = "2738--2741",

booktitle = "IEEE International Symposium on Circuits and Systems, ISCAS 2007",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 2007, ISCAS 2007 ; Conference date: 27-05-2007 Through 30-05-2007",

}

Qu, Y, Tiensyrjä, K, Soininen, J-P & Nurmi, J 2007, System-level design for partially reconfigurable hardware. in IEEE International Symposium on Circuits and Systems, ISCAS 2007. IEEE Institute of Electrical and Electronic Engineers, pp. 2738-2741, IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, United States, 27/05/07. https://doi.org/10.1109/ISCAS.2007.378619

System-level design for partially reconfigurable hardware. / Qu, Yang; Tiensyrjä, Kari; Soininen, Juha-Pekka et al.
IEEE International Symposium on Circuits and Systems, ISCAS 2007. IEEE Institute of Electrical and Electronic Engineers, 2007. p. 2738-2741.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - System-level design for partially reconfigurable hardware

AU - Qu, Yang

AU - Tiensyrjä, Kari

AU - Soininen, Juha-Pekka

AU - Nurmi, Jari

PY - 2007

Y1 - 2007

N2 - In this paper, we present a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.

AB - In this paper, we present a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.

KW - run-time reconfigurable hardware

KW - SystemC

KW - system-level design

U2 - 10.1109/ISCAS.2007.378619

DO - 10.1109/ISCAS.2007.378619

M3 - Conference article in proceedings

SN - 978-1-4244-0920-4

SP - 2738

EP - 2741

BT - IEEE International Symposium on Circuits and Systems, ISCAS 2007

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2007

Y2 - 27 May 2007 through 30 May 2007

ER -

System-level design for partially reconfigurable hardware

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Keywords

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