Abstract
This chapter describes the SystemC based modelling techniques and tools
that
support the design of reconfigurable systems-on-chip (SoC). For designing of
reconfigurable parts at system level, we developed: 1) an estimation method
and tool for estimating the execution time and the resource consumption of
function blocks on dynamically reconfigurable logic to support system
partitioning, 2) a SystemC based modeling method and tool for reconfigurable
parts to allow fast design space exploration through 3) system-level
simulation
using transaction-level models of the system.
| Original language | English |
|---|---|
| Title of host publication | System Level Design of Reconfigurable Systems-on-Chip |
| Editors | Nikolaos Voros, Konstantinos Masselos |
| Place of Publication | Dordrecht; NL |
| Publisher | Springer |
| Chapter | 5 |
| Pages | 107-131 |
| ISBN (Electronic) | 978-0-387-26104-1 |
| ISBN (Print) | 978-0-387-26103-4, 978-1-4419-3864-0 |
| Publication status | Published - 2005 |
| MoE publication type | D2 Article in professional manuals or guides or professional information systems or text book material |