Systems real time analysis with VHDL generated from graphical SA-VHDL

Matti Sipola, Juha-Pekka Soininen, Jorma Kivelä

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review


    This paper will demonstrate a method in which the high level system specification is defined using an user-friendly CASE tool together with VHSIC Hardware Description Language, VHDL. This method called SA-VHDL is especially suitable for system partitioning process of digital real-time embedded systems. A prototype tool SYS-RTA has been implemented to demonstrate the automatic conversion from the CASE tool output to the executable analysis model in VHDL. Simulation of the generated VHDL model reports the performance, i.e. response times, the resource usage, function activities and behavioural errors of the system. These results can be used for the quality analysis of the current system partitioning.
    Original languageEnglish
    Title of host publicationVHDL for Simulation, Synthesis and Formal Proofs of Hardware
    EditorsJean Mermet
    Place of PublicationStockholm
    PublisherKluwer Academic Publishers
    ISBN (Electronic)978-1-4615-3562-1
    ISBN (Print)978-1-4613-6582-2
    Publication statusPublished - 1991
    MoE publication typeA4 Article in a conference publication
    EventEURO-VHDL '91 2nd European Conference on VHDL Methods - Stockholm, Sweden
    Duration: 8 Sept 199111 Sept 1991

    Publication series

    SeriesThe Springer International Series in Engineering and Computer Science


    ConferenceEURO-VHDL '91 2nd European Conference on VHDL Methods


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