Systems real time analysis with VHDL generated from graphical SA-VHDL

Matti Sipola; Juha-Pekka Soininen; Jorma Kivelä

doi:10.1007/978-1-4615-3562-1_6

Systems real time analysis with VHDL generated from graphical SA-VHDL

Matti Sipola, Juha-Pekka Soininen, Jorma Kivelä

University of Oulu

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

This paper will demonstrate a method in which the high level system specification is defined using an user-friendly CASE tool together with VHSIC Hardware Description Language, VHDL. This method called SA-VHDL is especially suitable for system partitioning process of digital real-time embedded systems. A prototype tool SYS-RTA has been implemented to demonstrate the automatic conversion from the CASE tool output to the executable analysis model in VHDL. Simulation of the generated VHDL model reports the performance, i.e. response times, the resource usage, function activities and behavioural errors of the system. These results can be used for the quality analysis of the current system partitioning.

Original language	English
Title of host publication	VHDL for Simulation, Synthesis and Formal Proofs of Hardware
Editors	Jean Mermet
Place of Publication	Stockholm
Publisher	Kluwer Academic Publishers
Pages	32-38
ISBN (Electronic)	978-1-4615-3562-1
ISBN (Print)	978-1-4613-6582-2
DOIs	https://doi.org/10.1007/978-1-4615-3562-1_6
Publication status	Published - 1991
MoE publication type	A4 Article in a conference publication
Event	EURO-VHDL '91 2nd European Conference on VHDL Methods - Stockholm, Sweden Duration: 8 Sept 1991 → 11 Sept 1991

Publication series

Series	The Springer International Series in Engineering and Computer Science
Volume	183
ISSN	0893-3405

Conference

Conference	EURO-VHDL '91 2nd European Conference on VHDL Methods
Country/Territory	Sweden
City	Stockholm
Period	8/09/91 → 11/09/91

Access to Document

10.1007/978-1-4615-3562-1_6

Cite this

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title = "Systems real time analysis with VHDL generated from graphical SA-VHDL",

abstract = "This paper will demonstrate a method in which the high level system specification is defined using an user-friendly CASE tool together with VHSIC Hardware Description Language, VHDL. This method called SA-VHDL is especially suitable for system partitioning process of digital real-time embedded systems. A prototype tool SYS-RTA has been implemented to demonstrate the automatic conversion from the CASE tool output to the executable analysis model in VHDL. Simulation of the generated VHDL model reports the performance, i.e. response times, the resource usage, function activities and behavioural errors of the system. These results can be used for the quality analysis of the current system partitioning.",

author = "Matti Sipola and Juha-Pekka Soininen and Jorma Kivel{\"a}",

year = "1991",

doi = "10.1007/978-1-4615-3562-1_6",

language = "English",

isbn = "978-1-4613-6582-2",

series = "The Springer International Series in Engineering and Computer Science",

publisher = "Kluwer Academic Publishers",

pages = "32--38",

editor = "Jean Mermet",

booktitle = "VHDL for Simulation, Synthesis and Formal Proofs of Hardware",

address = "Netherlands",

note = "EURO-VHDL '91 2nd European Conference on VHDL Methods ; Conference date: 08-09-1991 Through 11-09-1991",

}

Sipola, M, Soininen, J-P & Kivelä, J 1991, Systems real time analysis with VHDL generated from graphical SA-VHDL. in J Mermet (ed.), VHDL for Simulation, Synthesis and Formal Proofs of Hardware. Kluwer Academic Publishers, Stockholm, The Springer International Series in Engineering and Computer Science, vol. 183, pp. 32-38, EURO-VHDL '91 2nd European Conference on VHDL Methods, Stockholm, Sweden, 8/09/91. https://doi.org/10.1007/978-1-4615-3562-1_6

Systems real time analysis with VHDL generated from graphical SA-VHDL. / Sipola, Matti; Soininen, Juha-Pekka; Kivelä, Jorma.
VHDL for Simulation, Synthesis and Formal Proofs of Hardware. ed. / Jean Mermet. Stockholm: Kluwer Academic Publishers, 1991. p. 32-38 (The Springer International Series in Engineering and Computer Science, Vol. 183).

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Systems real time analysis with VHDL generated from graphical SA-VHDL

AU - Sipola, Matti

AU - Soininen, Juha-Pekka

AU - Kivelä, Jorma

PY - 1991

Y1 - 1991

N2 - This paper will demonstrate a method in which the high level system specification is defined using an user-friendly CASE tool together with VHSIC Hardware Description Language, VHDL. This method called SA-VHDL is especially suitable for system partitioning process of digital real-time embedded systems. A prototype tool SYS-RTA has been implemented to demonstrate the automatic conversion from the CASE tool output to the executable analysis model in VHDL. Simulation of the generated VHDL model reports the performance, i.e. response times, the resource usage, function activities and behavioural errors of the system. These results can be used for the quality analysis of the current system partitioning.

AB - This paper will demonstrate a method in which the high level system specification is defined using an user-friendly CASE tool together with VHSIC Hardware Description Language, VHDL. This method called SA-VHDL is especially suitable for system partitioning process of digital real-time embedded systems. A prototype tool SYS-RTA has been implemented to demonstrate the automatic conversion from the CASE tool output to the executable analysis model in VHDL. Simulation of the generated VHDL model reports the performance, i.e. response times, the resource usage, function activities and behavioural errors of the system. These results can be used for the quality analysis of the current system partitioning.

U2 - 10.1007/978-1-4615-3562-1_6

DO - 10.1007/978-1-4615-3562-1_6

M3 - Conference article in proceedings

SN - 978-1-4613-6582-2

T3 - The Springer International Series in Engineering and Computer Science

SP - 32

EP - 38

BT - VHDL for Simulation, Synthesis and Formal Proofs of Hardware

A2 - Mermet, Jean

PB - Kluwer Academic Publishers

CY - Stockholm

T2 - EURO-VHDL '91 2nd European Conference on VHDL Methods

Y2 - 8 September 1991 through 11 September 1991

ER -

Systems real time analysis with VHDL generated from graphical SA-VHDL

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