Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS

Helena Pohjonen, Hannu Ronkainen, Marie-Louise Silen

    Research output: Book/ReportReport

    Abstract

    The development of the semiconductor processing needs test structures for individual processing steps and for combining the processing steps together to form finally a working process. The geometrical and electrical design rules are the link between the process and the design of the electrical structures. The test structures based on the proposed design rules can help electrical measurements to produce the final geometrical and electrical design rules. The report describes general test patterns for the oxide isolated self-aligned 5 um CMOS prosess. The test structures represented cover all the processing steps of the oxide isolated self-aligned CMOS process. Additional structures for measuring the scaling of the process are included. The possibility to use an additional material layer on the contact holes is also included.
    Original languageEnglish
    Place of PublicationEspoo
    PublisherVTT Technical Research Centre of Finland
    Number of pages111
    ISBN (Print)951-38-1981-7
    Publication statusPublished - 1984
    MoE publication typeD4 Published development or research report or study

    Publication series

    SeriesValtion teknillinen tutkimuskeskus. Tiedotteita
    Number350
    ISSN0358-5085

    Keywords

    • integrated circuits
    • semiconductor devices
    • design
    • testing
    • know-how

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  • Cite this

    Pohjonen, H., Ronkainen, H., & Silen, M-L. (1984). Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS. VTT Technical Research Centre of Finland. Valtion teknillinen tutkimuskeskus. Tiedotteita, No. 350