@book{ac2902bc31d040ba8c5cff8eab5a11f7,
title = "Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS",
abstract = "The development of the semiconductor processing needs test structures for individual processing steps and for combining the processing steps together to form finally a working process. The geometrical and electrical design rules are the link between the process and the design of the electrical structures. The test structures based on the proposed design rules can help electrical measurements to produce the final geometrical and electrical design rules. The report describes general test patterns for the oxide isolated self-aligned 5 um CMOS prosess. The test structures represented cover all the processing steps of the oxide isolated self-aligned CMOS process. Additional structures for measuring the scaling of the process are included. The possibility to use an additional material layer on the contact holes is also included.",
keywords = "integrated circuits, semiconductor devices, design, testing, know-how",
author = "Helena Pohjonen and Hannu Ronkainen and Marie-Louise Silen",
year = "1984",
language = "English",
isbn = "951-38-1981-7",
series = "Valtion teknillinen tutkimuskeskus. Tiedotteita",
publisher = "VTT Technical Research Centre of Finland",
number = "350",
address = "Finland",
}