Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS

Helena Pohjonen, Hannu Ronkainen, Marie-Louise Silen

    Research output: Book/ReportReport

    Abstract

    The development of the semiconductor processing needs test structures for individual processing steps and for combining the processing steps together to form finally a working process. The geometrical and electrical design rules are the link between the process and the design of the electrical structures. The test structures based on the proposed design rules can help electrical measurements to produce the final geometrical and electrical design rules. The report describes general test patterns for the oxide isolated self-aligned 5 um CMOS prosess. The test structures represented cover all the processing steps of the oxide isolated self-aligned CMOS process. Additional structures for measuring the scaling of the process are included. The possibility to use an additional material layer on the contact holes is also included.
    Original languageEnglish
    Place of PublicationEspoo
    PublisherVTT Technical Research Centre of Finland
    Number of pages111
    ISBN (Print)951-38-1981-7
    Publication statusPublished - 1984
    MoE publication typeD4 Published development or research report or study

    Publication series

    SeriesValtion teknillinen tutkimuskeskus. Tiedotteita
    Number350
    ISSN0358-5085

    Fingerprint

    Polysilicon
    Processing
    Oxides
    Semiconductor materials

    Keywords

    • integrated circuits
    • semiconductor devices
    • design
    • testing
    • know-how

    Cite this

    Pohjonen, H., Ronkainen, H., & Silen, M-L. (1984). Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS. Espoo: VTT Technical Research Centre of Finland. Valtion teknillinen tutkimuskeskus. Tiedotteita, No. 350
    Pohjonen, Helena ; Ronkainen, Hannu ; Silen, Marie-Louise. / Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS. Espoo : VTT Technical Research Centre of Finland, 1984. 111 p. (Valtion teknillinen tutkimuskeskus. Tiedotteita; No. 350).
    @book{ac2902bc31d040ba8c5cff8eab5a11f7,
    title = "Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS",
    abstract = "The development of the semiconductor processing needs test structures for individual processing steps and for combining the processing steps together to form finally a working process. The geometrical and electrical design rules are the link between the process and the design of the electrical structures. The test structures based on the proposed design rules can help electrical measurements to produce the final geometrical and electrical design rules. The report describes general test patterns for the oxide isolated self-aligned 5 um CMOS prosess. The test structures represented cover all the processing steps of the oxide isolated self-aligned CMOS process. Additional structures for measuring the scaling of the process are included. The possibility to use an additional material layer on the contact holes is also included.",
    keywords = "integrated circuits, semiconductor devices, design, testing, know-how",
    author = "Helena Pohjonen and Hannu Ronkainen and Marie-Louise Silen",
    year = "1984",
    language = "English",
    isbn = "951-38-1981-7",
    series = "Valtion teknillinen tutkimuskeskus. Tiedotteita",
    publisher = "VTT Technical Research Centre of Finland",
    number = "350",
    address = "Finland",

    }

    Pohjonen, H, Ronkainen, H & Silen, M-L 1984, Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS. Valtion teknillinen tutkimuskeskus. Tiedotteita, no. 350, VTT Technical Research Centre of Finland, Espoo.

    Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS. / Pohjonen, Helena; Ronkainen, Hannu; Silen, Marie-Louise.

    Espoo : VTT Technical Research Centre of Finland, 1984. 111 p. (Valtion teknillinen tutkimuskeskus. Tiedotteita; No. 350).

    Research output: Book/ReportReport

    TY - BOOK

    T1 - Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS

    AU - Pohjonen, Helena

    AU - Ronkainen, Hannu

    AU - Silen, Marie-Louise

    PY - 1984

    Y1 - 1984

    N2 - The development of the semiconductor processing needs test structures for individual processing steps and for combining the processing steps together to form finally a working process. The geometrical and electrical design rules are the link between the process and the design of the electrical structures. The test structures based on the proposed design rules can help electrical measurements to produce the final geometrical and electrical design rules. The report describes general test patterns for the oxide isolated self-aligned 5 um CMOS prosess. The test structures represented cover all the processing steps of the oxide isolated self-aligned CMOS process. Additional structures for measuring the scaling of the process are included. The possibility to use an additional material layer on the contact holes is also included.

    AB - The development of the semiconductor processing needs test structures for individual processing steps and for combining the processing steps together to form finally a working process. The geometrical and electrical design rules are the link between the process and the design of the electrical structures. The test structures based on the proposed design rules can help electrical measurements to produce the final geometrical and electrical design rules. The report describes general test patterns for the oxide isolated self-aligned 5 um CMOS prosess. The test structures represented cover all the processing steps of the oxide isolated self-aligned CMOS process. Additional structures for measuring the scaling of the process are included. The possibility to use an additional material layer on the contact holes is also included.

    KW - integrated circuits

    KW - semiconductor devices

    KW - design

    KW - testing

    KW - know-how

    M3 - Report

    SN - 951-38-1981-7

    T3 - Valtion teknillinen tutkimuskeskus. Tiedotteita

    BT - Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS

    PB - VTT Technical Research Centre of Finland

    CY - Espoo

    ER -

    Pohjonen H, Ronkainen H, Silen M-L. Test structure for the local oxidized self-aligned polysilicon gate CMOS process, NORDIC MOS. Espoo: VTT Technical Research Centre of Finland, 1984. 111 p. (Valtion teknillinen tutkimuskeskus. Tiedotteita; No. 350).