Abstract
General purpose chip multiprocessors (CMP) are
challenging to on-chip intercommunication network
designers since one would need low latency, high
bandwidth independently of the communication patterns,
support for cost-efficient synchronization, and low
energy consumption to support arbitrary applications.
Currently popular ring-based networks provide
straight-forward design, far superior performance than
bus-based alternatives and extensibility over crossbars.
As the number of processors cores increases, however, the
effective bandwidth between most parts of a ring remains
constant implying higher capacity solutions are needed to
support scaled-up CMPs. In this paper we describe the
on-chip network of our REPLICA CMP. It is based on an
acyclic bandwidth-scaled multi-mesh topology and uses
routing with elastic synchronization mechanism. To avoid
congestion and hot spots in shared memory access traffic
can be randomized with a programmable hashing function.
The performance of the network is evaluated preliminarily
on our experimental 4-core and 16-core REPLICA FPGA
implementations and REPLICA simulator.
| Original language | English |
|---|---|
| Title of host publication | Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE |
| Publisher | IEEE Institute of Electrical and Electronic Engineers |
| Pages | 1 - 6 |
| ISBN (Electronic) | 978-1-5090-1095-0 |
| ISBN (Print) | 978-1-5090-1096-7 |
| DOIs | |
| Publication status | Published - 22 Dec 2016 |
| MoE publication type | A4 Article in a conference publication |
| Event | IEEE Nordic Circuits and Systems Conference - Copenhagen, Denmark Duration: 1 Nov 2016 → 2 Nov 2016 Conference number: 2 |
Conference
| Conference | IEEE Nordic Circuits and Systems Conference |
|---|---|
| Abbreviated title | NORCAS |
| Country/Territory | Denmark |
| City | Copenhagen |
| Period | 1/11/16 → 2/11/16 |
Keywords
- chip multiprocessor
- hashing
- network on chip
- Parallel computing
- routing
- synchronization
- topology