The REPLICA on-chip network

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

Abstract

General purpose chip multiprocessors (CMP) are challenging to on-chip intercommunication network designers since one would need low latency, high bandwidth independently of the communication patterns, support for cost-efficient synchronization, and low energy consumption to support arbitrary applications. Currently popular ring-based networks provide straight-forward design, far superior performance than bus-based alternatives and extensibility over crossbars. As the number of processors cores increases, however, the effective bandwidth between most parts of a ring remains constant implying higher capacity solutions are needed to support scaled-up CMPs. In this paper we describe the on-chip network of our REPLICA CMP. It is based on an acyclic bandwidth-scaled multi-mesh topology and uses routing with elastic synchronization mechanism. To avoid congestion and hot spots in shared memory access traffic can be randomized with a programmable hashing function. The performance of the network is evaluated preliminarily on our experimental 4-core and 16-core REPLICA FPGA implementations and REPLICA simulator.
Original languageEnglish
Title of host publicationNordic Circuits and Systems Conference (NORCAS), 2016 IEEE
PublisherInstitute of Electrical and Electronic Engineers IEEE
Pages1 - 6
ISBN (Electronic)978-1-5090-1095-0
ISBN (Print)978-1-5090-1096-7
DOIs
Publication statusPublished - 22 Dec 2016
MoE publication typeA4 Article in a conference publication
EventIEEE Nordic Circuits and Systems Conference - Copenhagen, Denmark
Duration: 1 Nov 20162 Nov 2016
Conference number: 2

Conference

ConferenceIEEE Nordic Circuits and Systems Conference
Abbreviated titleNORCAS
CountryDenmark
CityCopenhagen
Period1/11/162/11/16

Fingerprint

Bandwidth
Synchronization
Field programmable gate arrays (FPGA)
Energy utilization
Simulators
Topology
Data storage equipment
Communication
Network-on-chip
Costs

Keywords

  • chip multiprocessor
  • hashing
  • network on chip
  • Parallel computing
  • routing
  • synchronization
  • topology

Cite this

Forsell, M., Roivainen, J., & Leppänen, V. (2016). The REPLICA on-chip network. In Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE (pp. 1 - 6). Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/NORCHIP.2016.7792877
Forsell, Martti ; Roivainen, Jussi ; Leppänen, Ville. / The REPLICA on-chip network. Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE. Institute of Electrical and Electronic Engineers IEEE, 2016. pp. 1 - 6
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Forsell, M, Roivainen, J & Leppänen, V 2016, The REPLICA on-chip network. in Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE. Institute of Electrical and Electronic Engineers IEEE, pp. 1 - 6, IEEE Nordic Circuits and Systems Conference, Copenhagen, Denmark, 1/11/16. https://doi.org/10.1109/NORCHIP.2016.7792877

The REPLICA on-chip network. / Forsell, Martti; Roivainen, Jussi; Leppänen, Ville.

Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE. Institute of Electrical and Electronic Engineers IEEE, 2016. p. 1 - 6.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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Forsell M, Roivainen J, Leppänen V. The REPLICA on-chip network. In Nordic Circuits and Systems Conference (NORCAS), 2016 IEEE. Institute of Electrical and Electronic Engineers IEEE. 2016. p. 1 - 6 https://doi.org/10.1109/NORCHIP.2016.7792877