Thermal detector and thermal detector array

Aapo Varpula (Inventor), Bin Guo (Inventor)

    Research output: PatentPatent


    A wafer-level integrated thermal detector comprises a first wafer and a second wafer (W1, W2) bonded together. The first wafer (W1) includes a dielectric or semiconducting substrate (100), a dielectric sacrificial layer (102) deposited on the substrate, a support layer (104) deposited on the sacrificial layer or the substrate, a suspended active element (108) provided within an opening (106) in the support layer, a first vacuum-sealed cavity (110) and a second vacuum-sealed cavity (106) on opposite sides of the suspended active element. The first vacuum-sealed cavity (110) extends into the sacrificial layer (102) at the location of the suspended active element (108). The second vacuum-sealed cavity (106) comprises the opening of the support layer (104) closed by the bonded second wafer. The thermal detector further comprises front optics (120) for entrance of radiation from outside into one of the first and second vacuum-sealed cavities, aback reflector (112) arranged to reflect radiation back into the other one of the first and second vacuum-sealed cavities, and electrical connections (114) for connecting the suspended active element to a readout circuit (118).

    Patent family as of 29.12.2021
    CN111356907 A 20200630 CN201880070853 20180831      
    EP3676584 A1 20200708 EP20180769414 20180831      
    JP2020531861 T2 20201105 JP20200512595T 20180831      
    US11199455 BB 20211214 US20200642939 20180831      
    US2020309603 AA 20201001 US20200642939 20180831      
    WO19043299 A1 20190307 WO2018FI50619 20180831

    Link to current patent family on right 

    Original languageEnglish
    Patent numberEP3676584
    IPCG01J 5/ 20 A I
    Priority date31/08/18
    Publication statusPublished - 8 Jul 2020
    MoE publication typeH1 Granted patent


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