Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture

Jari-Matti Mäkelä; Ville Leppänen; Martti Forsell

doi:10.1145/2516775.2516818

Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture

Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell

University of Turku

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

1 Citation (Scopus)

Abstract

Modern chip-multiprocessors pack an increasing amount of computational cores with each generation. Along with new computational power comes a problem of managing a large pool of active threads. Traditional debuggers often deal with concurrency style multi-threading with emphasis on a single thread. The problem of thread management when debugging parallel programs is analyzed and solutions are suggested. A related debugging framework for the massively multi-threaded, synchronous REPLICA architecture is proposed.

Original language	English
Title of host publication	CompSysTech '13
Subtitle of host publication	Proceedings of the 14th International Conference on Computer Systems and Technologies
Editors	Boris Rachev, Angel Smrikarov
Place of Publication	New York
Publisher	Association for Computing Machinery ACM
Pages	153-160
ISBN (Print)	978-1-4503-2021-4
DOIs	https://doi.org/10.1145/2516775.2516818
Publication status	Published - 2013
MoE publication type	A4 Article in a conference publication
Event	14th International Conference on Computer Systems and Technologies, CompSysTech 2013 - Ruse, Bulgaria Duration: 28 Jun 2013 → 29 Jun 2013

Conference

Conference	14th International Conference on Computer Systems and Technologies, CompSysTech 2013
Abbreviated title	CompSysTech 2013
Country/Territory	Bulgaria
City	Ruse
Period	28/06/13 → 29/06/13

Keywords

debuggin
multi-core
parallel computing
processor architecture

Access to Document

10.1145/2516775.2516818

Cite this

Mäkelä, J.-M., Leppänen, V., & Forsell, M. (2013). Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. In B. Rachev, & A. Smrikarov (Eds.), CompSysTech '13 : Proceedings of the 14th International Conference on Computer Systems and Technologies (pp. 153-160). Association for Computing Machinery ACM. https://doi.org/10.1145/2516775.2516818

Mäkelä, Jari-Matti ; Leppänen, Ville ; Forsell, Martti. / Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. CompSysTech '13 : Proceedings of the 14th International Conference on Computer Systems and Technologies. editor / Boris Rachev ; Angel Smrikarov. New York : Association for Computing Machinery ACM, 2013. pp. 153-160

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abstract = "Modern chip-multiprocessors pack an increasing amount of computational cores with each generation. Along with new computational power comes a problem of managing a large pool of active threads. Traditional debuggers often deal with concurrency style multi-threading with emphasis on a single thread. The problem of thread management when debugging parallel programs is analyzed and solutions are suggested. A related debugging framework for the massively multi-threaded, synchronous REPLICA architecture is proposed.",

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Mäkelä, J-M, Leppänen, V & Forsell, M 2013, Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. in B Rachev & A Smrikarov (eds), CompSysTech '13 : Proceedings of the 14th International Conference on Computer Systems and Technologies. Association for Computing Machinery ACM, New York, pp. 153-160, 14th International Conference on Computer Systems and Technologies, CompSysTech 2013, Ruse, Bulgaria, 28/06/13. https://doi.org/10.1145/2516775.2516818

Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. / Mäkelä, Jari-Matti; Leppänen, Ville; Forsell, Martti.
CompSysTech '13 : Proceedings of the 14th International Conference on Computer Systems and Technologies. ed. / Boris Rachev; Angel Smrikarov. New York: Association for Computing Machinery ACM, 2013. p. 153-160.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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PY - 2013

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N2 - Modern chip-multiprocessors pack an increasing amount of computational cores with each generation. Along with new computational power comes a problem of managing a large pool of active threads. Traditional debuggers often deal with concurrency style multi-threading with emphasis on a single thread. The problem of thread management when debugging parallel programs is analyzed and solutions are suggested. A related debugging framework for the massively multi-threaded, synchronous REPLICA architecture is proposed.

AB - Modern chip-multiprocessors pack an increasing amount of computational cores with each generation. Along with new computational power comes a problem of managing a large pool of active threads. Traditional debuggers often deal with concurrency style multi-threading with emphasis on a single thread. The problem of thread management when debugging parallel programs is analyzed and solutions are suggested. A related debugging framework for the massively multi-threaded, synchronous REPLICA architecture is proposed.

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KW - multi-core

KW - parallel computing

KW - processor architecture

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DO - 10.1145/2516775.2516818

M3 - Conference article in proceedings

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T2 - 14th International Conference on Computer Systems and Technologies, CompSysTech 2013

Y2 - 28 June 2013 through 29 June 2013

ER -

Mäkelä JM, Leppänen V, Forsell M. Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. In Rachev B, Smrikarov A, editors, CompSysTech '13 : Proceedings of the 14th International Conference on Computer Systems and Technologies. New York: Association for Computing Machinery ACM. 2013. p. 153-160 doi: 10.1145/2516775.2516818

Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture

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