Transport Triggered Array Processor for Vision Applications

Safarpour Mehdi (Corresponding author), Hautala Ilkka, Miguel Bordallo López, Olli Silvén

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

1 Citation (Scopus)


Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, ultra-low-leakage processes are employed in fabrication. Those limit the clocking rates significantly, reducing the computing throughputs of individual cores. In this contribution we explore compensating for the substantial computing power needs of a vision application using massive parallelism. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations.
Original languageEnglish
Title of host publicationEmbedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019
EditorsMaxime Pelcat, Matthias Jung, Dionisios N. Pnevmatikatos
Number of pages12
ISBN (Electronic)978-3-030-27562-4
ISBN (Print)978-3-030-27561-7
Publication statusPublished - 2019
MoE publication typeA4 Article in a conference publication
Event19th International Conference on Embedded Computer Systems, SAmos 2019 - Samos, Greece
Duration: 7 Jul 201911 Jul 2019

Publication series

SeriesLecture Notes in Computer Science


Conference19th International Conference on Embedded Computer Systems, SAmos 2019


  • Binary Patterns
  • Computer vision
  • Embedded systems
  • Internet-of-Things
  • Massive processing arrays


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