Transport Triggered Array Processor for Vision Applications

Safarpour Mehdi; Hautala Ilkka; Miguel Bordallo López; Olli Silvén

doi:10.1007/978-3-030-27562-4_26

Transport Triggered Array Processor for Vision Applications

Safarpour Mehdi (Corresponding author), Hautala Ilkka, Miguel Bordallo López, Olli Silvén

Not published at VTT

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, ultra-low-leakage processes are employed in fabrication. Those limit the clocking rates significantly, reducing the computing throughputs of individual cores. In this contribution we explore compensating for the substantial computing power needs of a vision application using massive parallelism. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations.

Original language	English
Title of host publication	Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019
Editors	Maxime Pelcat, Matthias Jung, Dionisios N. Pnevmatikatos
Publisher	Springer
Pages	361-372
Number of pages	12
ISBN (Electronic)	978-3-030-27562-4
ISBN (Print)	978-3-030-27561-7
DOIs	https://doi.org/10.1007/978-3-030-27562-4_26
Publication status	Published - 2019
MoE publication type	A4 Article in a conference publication
Event	19th International Conference on Embedded Computer Systems, SAmos 2019 - Samos, Greece Duration: 7 Jul 2019 → 11 Jul 2019

Publication series

Series	Lecture Notes in Computer Science
Volume	11733
ISSN	0302-9743

Conference

Conference	19th International Conference on Embedded Computer Systems, SAmos 2019
Country	Greece
City	Samos
Period	7/07/19 → 11/07/19

Keywords

Binary Patterns
Computer vision
Embedded systems
Internet-of-Things
Massive processing arrays

UN SDGs

This output contributes to the following Sustainable Development Goal(s)

Access to Document

10.1007/978-3-030-27562-4_26

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Mehdi, S., Ilkka, H., Bordallo López, M., & Silvén, O. (2019). Transport Triggered Array Processor for Vision Applications. In M. Pelcat, M. Jung, & D. N. Pnevmatikatos (Eds.), Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019 (pp. 361-372). Springer. Lecture Notes in Computer Science Vol. 11733 https://doi.org/10.1007/978-3-030-27562-4_26

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title = "Transport Triggered Array Processor for Vision Applications",

abstract = "Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, ultra-low-leakage processes are employed in fabrication. Those limit the clocking rates significantly, reducing the computing throughputs of individual cores. In this contribution we explore compensating for the substantial computing power needs of a vision application using massive parallelism. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations.",

keywords = "Binary Patterns, Computer vision, Embedded systems, Internet-of-Things, Massive processing arrays",

author = "Safarpour Mehdi and Hautala Ilkka and {Bordallo L{\'o}pez}, Miguel and Olli Silv{\'e}n",

year = "2019",

doi = "10.1007/978-3-030-27562-4_26",

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booktitle = "Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019",

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Mehdi, S, Ilkka, H, Bordallo López, M & Silvén, O 2019, Transport Triggered Array Processor for Vision Applications. in M Pelcat, M Jung & DN Pnevmatikatos (eds), Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019. Springer, Lecture Notes in Computer Science, vol. 11733, pp. 361-372, 19th International Conference on Embedded Computer Systems, SAmos 2019, Samos, Greece, 7/07/19. https://doi.org/10.1007/978-3-030-27562-4_26

Transport Triggered Array Processor for Vision Applications. / Mehdi, Safarpour (Corresponding author); Ilkka, Hautala; Bordallo López, Miguel; Silvén, Olli.

Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2019. ed. / Maxime Pelcat; Matthias Jung; Dionisios N. Pnevmatikatos. Springer, 2019. p. 361-372 (Lecture Notes in Computer Science, Vol. 11733).

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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AU - Mehdi, Safarpour

AU - Ilkka, Hautala

AU - Bordallo López, Miguel

AU - Silvén, Olli

PY - 2019

Y1 - 2019

N2 - Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, ultra-low-leakage processes are employed in fabrication. Those limit the clocking rates significantly, reducing the computing throughputs of individual cores. In this contribution we explore compensating for the substantial computing power needs of a vision application using massive parallelism. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations.

AB - Low-level sensory data processing in many Internet-of-Things (IoT) devices pursue energy efficiency by utilizing sleep modes or slowing the clocking to the minimum. To curb the share of stand-by power dissipation in those designs, ultra-low-leakage processes are employed in fabrication. Those limit the clocking rates significantly, reducing the computing throughputs of individual cores. In this contribution we explore compensating for the substantial computing power needs of a vision application using massive parallelism. The Processing Elements (PE) of the design are based on Transport Triggered Architecture. The fine grained programmable parallel solution allows for fast and efficient computation of learnable low-level features (e.g. local binary descriptors and convolutions). Other operations, including Max-pooling have also been implemented. The programmable design achieves excellent energy efficiency for Local Binary Patterns computations.

KW - Binary Patterns

KW - Computer vision

KW - Embedded systems

KW - Internet-of-Things

KW - Massive processing arrays

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PB - Springer

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Y2 - 7 July 2019 through 11 July 2019

ER -

Transport Triggered Array Processor for Vision Applications

Abstract

Publication series

Conference

Keywords

UN SDGs

Access to Document

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