Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Mikko Kaltiokallio, Jani Mäkipää, Arto Rantala, Matti Sopanen

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    1 Citation (Scopus)

    Abstract

    To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.
    Original languageEnglish
    Title of host publicationProceedings
    Subtitle of host publicationSOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Number of pages2
    ISBN (Electronic)978-1-4799-7439-9
    ISBN (Print)978-1-4799-7438-2
    DOIs
    Publication statusPublished - 2014
    MoE publication typeA4 Article in a conference publication
    EventIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 - Millbrae, CA, United Kingdom
    Duration: 6 Oct 20149 Oct 2014

    Conference

    ConferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
    Abbreviated titleS3S 2014
    CountryUnited Kingdom
    CityMillbrae, CA
    Period6/10/149/10/14

    Fingerprint

    Reduced instruction set computing
    Program processors
    Energy utilization
    Digital circuits
    Electric potential
    Application specific integrated circuits
    Threshold voltage
    Stretching
    Energy efficiency
    Clocks
    Energy conservation

    Cite this

    Hiienkari, M., Teittinen, J., Koskinen, L., Turnquist, M., Kaltiokallio, M., Mäkipää, J., ... Sopanen, M. (2014). Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. In Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 [7028192] IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/S3S.2014.7028192
    Hiienkari, Markus ; Teittinen, Jukka ; Koskinen, Lauri ; Turnquist, Matthew ; Kaltiokallio, Mikko ; Mäkipää, Jani ; Rantala, Arto ; Sopanen, Matti. / Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. IEEE Institute of Electrical and Electronic Engineers , 2014.
    @inproceedings{b29dd3c0508847bea364c15053d1cdda,
    title = "Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS",
    abstract = "To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39{\%} energy savings and 83{\%} EDP improvement compared to operation based on static signoff timing.",
    author = "Markus Hiienkari and Jukka Teittinen and Lauri Koskinen and Matthew Turnquist and Mikko Kaltiokallio and Jani M{\"a}kip{\"a}{\"a} and Arto Rantala and Matti Sopanen",
    year = "2014",
    doi = "10.1109/S3S.2014.7028192",
    language = "English",
    isbn = "978-1-4799-7438-2",
    booktitle = "Proceedings",
    publisher = "IEEE Institute of Electrical and Electronic Engineers",
    address = "United States",

    }

    Hiienkari, M, Teittinen, J, Koskinen, L, Turnquist, M, Kaltiokallio, M, Mäkipää, J, Rantala, A & Sopanen, M 2014, Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. in Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014., 7028192, IEEE Institute of Electrical and Electronic Engineers , IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014, Millbrae, CA, United Kingdom, 6/10/14. https://doi.org/10.1109/S3S.2014.7028192

    Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. / Hiienkari, Markus; Teittinen, Jukka; Koskinen, Lauri; Turnquist, Matthew; Kaltiokallio, Mikko; Mäkipää, Jani; Rantala, Arto; Sopanen, Matti.

    Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. IEEE Institute of Electrical and Electronic Engineers , 2014. 7028192.

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    TY - GEN

    T1 - Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

    AU - Hiienkari, Markus

    AU - Teittinen, Jukka

    AU - Koskinen, Lauri

    AU - Turnquist, Matthew

    AU - Kaltiokallio, Mikko

    AU - Mäkipää, Jani

    AU - Rantala, Arto

    AU - Sopanen, Matti

    PY - 2014

    Y1 - 2014

    N2 - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

    AB - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

    U2 - 10.1109/S3S.2014.7028192

    DO - 10.1109/S3S.2014.7028192

    M3 - Conference article in proceedings

    SN - 978-1-4799-7438-2

    BT - Proceedings

    PB - IEEE Institute of Electrical and Electronic Engineers

    ER -

    Hiienkari M, Teittinen J, Koskinen L, Turnquist M, Kaltiokallio M, Mäkipää J et al. Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. In Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. IEEE Institute of Electrical and Electronic Engineers . 2014. 7028192 https://doi.org/10.1109/S3S.2014.7028192