Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Mikko Kaltiokallio, Jani Mäkipää, Arto Rantala, Matti Sopanen

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

1 Citation (Scopus)

Abstract

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.
Original languageEnglish
Title of host publicationProceedings
Subtitle of host publicationSOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
PublisherInstitute of Electrical and Electronic Engineers IEEE
Number of pages2
ISBN (Electronic)978-1-4799-7439-9
ISBN (Print)978-1-4799-7438-2
DOIs
Publication statusPublished - 2014
MoE publication typeA4 Article in a conference publication
EventIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 - Millbrae, CA, United Kingdom
Duration: 6 Oct 20149 Oct 2014

Conference

ConferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
Abbreviated titleS3S 2014
CountryUnited Kingdom
CityMillbrae, CA
Period6/10/149/10/14

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Reduced instruction set computing
Program processors
Energy utilization
Digital circuits
Electric potential
Application specific integrated circuits
Threshold voltage
Stretching
Energy efficiency
Clocks
Energy conservation

Cite this

Hiienkari, M., Teittinen, J., Koskinen, L., Turnquist, M., Kaltiokallio, M., Mäkipää, J., ... Sopanen, M. (2014). Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. In Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 [7028192] Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/S3S.2014.7028192
Hiienkari, Markus ; Teittinen, Jukka ; Koskinen, Lauri ; Turnquist, Matthew ; Kaltiokallio, Mikko ; Mäkipää, Jani ; Rantala, Arto ; Sopanen, Matti. / Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. Institute of Electrical and Electronic Engineers IEEE, 2014.
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abstract = "To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39{\%} energy savings and 83{\%} EDP improvement compared to operation based on static signoff timing.",
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Hiienkari, M, Teittinen, J, Koskinen, L, Turnquist, M, Kaltiokallio, M, Mäkipää, J, Rantala, A & Sopanen, M 2014, Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. in Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014., 7028192, Institute of Electrical and Electronic Engineers IEEE, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014, Millbrae, CA, United Kingdom, 6/10/14. https://doi.org/10.1109/S3S.2014.7028192

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. / Hiienkari, Markus; Teittinen, Jukka; Koskinen, Lauri; Turnquist, Matthew; Kaltiokallio, Mikko; Mäkipää, Jani; Rantala, Arto; Sopanen, Matti.

Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. Institute of Electrical and Electronic Engineers IEEE, 2014. 7028192.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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AU - Hiienkari, Markus

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AU - Koskinen, Lauri

AU - Turnquist, Matthew

AU - Kaltiokallio, Mikko

AU - Mäkipää, Jani

AU - Rantala, Arto

AU - Sopanen, Matti

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N2 - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

AB - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

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Hiienkari M, Teittinen J, Koskinen L, Turnquist M, Kaltiokallio M, Mäkipää J et al. Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. In Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. Institute of Electrical and Electronic Engineers IEEE. 2014. 7028192 https://doi.org/10.1109/S3S.2014.7028192