Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Markus Hiienkari; Jukka Teittinen; Lauri Koskinen; Matthew Turnquist; Mikko Kaltiokallio; Jani Mäkipää; Arto Rantala; Matti Sopanen

doi:10.1109/S3S.2014.7028192

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Markus Hiienkari
, Jukka Teittinen
, Lauri Koskinen
, Matthew Turnquist
, Mikko Kaltiokallio
, Jani Mäkipää
, Arto Rantala
, Matti Sopanen

University of Turku
Aalto University

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

1 Citation (Scopus)

Abstract

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

Original language	English
Title of host publication	Proceedings
Subtitle of host publication	SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
Publisher	IEEE Institute of Electrical and Electronic Engineers
Number of pages	2
ISBN (Electronic)	978-1-4799-7439-9
ISBN (Print)	978-1-4799-7438-2
DOIs	https://doi.org/10.1109/S3S.2014.7028192
Publication status	Published - 2014
MoE publication type	A4 Article in a conference publication
Event	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 - Millbrae, CA, United Kingdom Duration: 6 Oct 2014 → 9 Oct 2014

Conference

Conference	IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014
Abbreviated title	S3S 2014
Country/Territory	United Kingdom
City	Millbrae, CA
Period	6/10/14 → 9/10/14

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/S3S.2014.7028192

Cite this

Hiienkari, M., Teittinen, J., Koskinen, L., Turnquist, M., Kaltiokallio, M., Mäkipää, J., Rantala, A., & Sopanen, M. (2014). Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. In Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 Article 7028192 IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/S3S.2014.7028192

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title = "Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS",

abstract = "To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39\% energy savings and 83\% EDP improvement compared to operation based on static signoff timing.",

author = "Markus Hiienkari and Jukka Teittinen and Lauri Koskinen and Matthew Turnquist and Mikko Kaltiokallio and Jani M{\"a}kip{\"a}{\"a} and Arto Rantala and Matti Sopanen",

year = "2014",

doi = "10.1109/S3S.2014.7028192",

language = "English",

isbn = "978-1-4799-7438-2",

booktitle = "Proceedings",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014, S3S 2014 ; Conference date: 06-10-2014 Through 09-10-2014",

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Hiienkari, M, Teittinen, J, Koskinen, L, Turnquist, M, Kaltiokallio, M, Mäkipää, J, Rantala, A & Sopanen, M 2014, Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. in Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014., 7028192, IEEE Institute of Electrical and Electronic Engineers, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014, Millbrae, CA, United Kingdom, 6/10/14. https://doi.org/10.1109/S3S.2014.7028192

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS. / Hiienkari, Markus; Teittinen, Jukka; Koskinen, Lauri et al.
Proceedings: SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014. IEEE Institute of Electrical and Electronic Engineers, 2014. 7028192.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

AU - Hiienkari, Markus

AU - Teittinen, Jukka

AU - Koskinen, Lauri

AU - Turnquist, Matthew

AU - Kaltiokallio, Mikko

AU - Mäkipää, Jani

AU - Rantala, Arto

AU - Sopanen, Matti

PY - 2014

Y1 - 2014

N2 - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

AB - To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

U2 - 10.1109/S3S.2014.7028192

DO - 10.1109/S3S.2014.7028192

M3 - Conference article in proceedings

SN - 978-1-4799-7438-2

BT - Proceedings

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014

Y2 - 6 October 2014 through 9 October 2014

ER -

Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Abstract

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UN SDGs

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