Use of electrical test structures to characterize trench profiles etched on SOI wafers

Jyrki Kiihamäki, Hannu Kattelus, Jani Karttunen, Nadine Guillaume

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    2 Citations (Scopus)

    Abstract

    This paper demonstrates the use of electrical test structures patterned on silicon-on-insulator (SOI) material to evaluate the performance of the plasma etching process. Electrical characterization is performed by capacitance and resistance measurements. The measurements are used to compare the etch results of slightly varied plasma etch processes. Subtle differences in submicron trench profiles are very difficult to distinguish and quantify when using scanning electron microscopy (SEM). The electrical measurements can reveal these differences, facilitating etch process development. Experimental results are presented and compared to cross-sectional SEM analysis. The goal of the development of test structures presented here is to establish a fast, low cost, and nondestructive method to characterize and optimize deep trench etching process cycles needed in the fabrication of micromachined devices.
    Original languageEnglish
    Title of host publicationICMTS 2001: Proceedings of the 2001 International Conference on Microelectronic Test Structures
    Subtitle of host publicationKobe, Japan, 19-22 March 2001
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages159-164
    ISBN (Print)0-7803-6511-9
    DOIs
    Publication statusPublished - 2001
    MoE publication typeA4 Article in a conference publication

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