Vacuum packaging at wafer level for MEMS using gold-tin metallurgy

C.-A. Manier, K. Zoschke, H. Oppermann, D. Ruffieux, S Dalla Piazza, Tommi Suni, James Dekker, G. Allegato

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

1 Citation (Scopus)

Abstract

Results of wafer level packaging for micro-electro-mechanical systems based on low temperature melting metallurgy are going to be presented. The MEMS are packaged under vacuum with internal pressure in the range of 1 mbar after sealing. Through Silicon Vias in a silicon interposer allow the feeding of the electrical contacts to the package outside. The thin silicon interposer acts as MEMS carrier or lid and therefore is part of the final packaged component after dicing. AuSn rings have been chosen for process compatibility with the MEMS and ensure the hermeticity of the components after vacuum sealing. Evaluation of the bond process is carried out using XRay imaging microscopy, analysis of cross sections and the final package resistance is evaluated using shear testing. The thickness of the chip-scale packaged MEMS is smaller than 500 µm and a yield of vacuum sealing of around 80% was obtained in first evaluation on 200 mm wafer scale
Original languageEnglish
Title of host publication2013 European Microelectronics Packaging Conference (EMPC)
PublisherIEEE Institute of Electrical and Electronic Engineers
Number of pages8
ISBN (Print)978-2-9527-4671-7
Publication statusPublished - 2013
MoE publication typeA4 Article in a conference publication
EventEMPC 2013: European Microelectronics and Packaging Conference - Grenoble, France
Duration: 9 Sep 201312 Sep 2013

Conference

ConferenceEMPC 2013
CountryFrance
CityGrenoble
Period9/09/1312/09/13

Fingerprint

metallurgy
packaging
microelectromechanical systems
tin
sealing
wafers
gold
vacuum
silicon
internal pressure
evaluation
compatibility
electric contacts
chips
melting
shear
microscopy
rings
cross sections

Keywords

  • Au/Sn
  • interposer
  • MEMS
  • sealing
  • vacuum
  • WLP

Cite this

Manier, C-A., Zoschke, K., Oppermann, H., Ruffieux, D., Dalla Piazza, S., Suni, T., ... Allegato, G. (2013). Vacuum packaging at wafer level for MEMS using gold-tin metallurgy. In 2013 European Microelectronics Packaging Conference (EMPC) [6698698] IEEE Institute of Electrical and Electronic Engineers .
Manier, C.-A. ; Zoschke, K. ; Oppermann, H. ; Ruffieux, D. ; Dalla Piazza, S ; Suni, Tommi ; Dekker, James ; Allegato, G. / Vacuum packaging at wafer level for MEMS using gold-tin metallurgy. 2013 European Microelectronics Packaging Conference (EMPC). IEEE Institute of Electrical and Electronic Engineers , 2013.
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abstract = "Results of wafer level packaging for micro-electro-mechanical systems based on low temperature melting metallurgy are going to be presented. The MEMS are packaged under vacuum with internal pressure in the range of 1 mbar after sealing. Through Silicon Vias in a silicon interposer allow the feeding of the electrical contacts to the package outside. The thin silicon interposer acts as MEMS carrier or lid and therefore is part of the final packaged component after dicing. AuSn rings have been chosen for process compatibility with the MEMS and ensure the hermeticity of the components after vacuum sealing. Evaluation of the bond process is carried out using XRay imaging microscopy, analysis of cross sections and the final package resistance is evaluated using shear testing. The thickness of the chip-scale packaged MEMS is smaller than 500 µm and a yield of vacuum sealing of around 80{\%} was obtained in first evaluation on 200 mm wafer scale",
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Manier, C-A, Zoschke, K, Oppermann, H, Ruffieux, D, Dalla Piazza, S, Suni, T, Dekker, J & Allegato, G 2013, Vacuum packaging at wafer level for MEMS using gold-tin metallurgy. in 2013 European Microelectronics Packaging Conference (EMPC)., 6698698, IEEE Institute of Electrical and Electronic Engineers , EMPC 2013, Grenoble, France, 9/09/13.

Vacuum packaging at wafer level for MEMS using gold-tin metallurgy. / Manier, C.-A.; Zoschke, K.; Oppermann, H.; Ruffieux, D.; Dalla Piazza, S; Suni, Tommi; Dekker, James; Allegato, G.

2013 European Microelectronics Packaging Conference (EMPC). IEEE Institute of Electrical and Electronic Engineers , 2013. 6698698.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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AU - Manier, C.-A.

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AU - Suni, Tommi

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N2 - Results of wafer level packaging for micro-electro-mechanical systems based on low temperature melting metallurgy are going to be presented. The MEMS are packaged under vacuum with internal pressure in the range of 1 mbar after sealing. Through Silicon Vias in a silicon interposer allow the feeding of the electrical contacts to the package outside. The thin silicon interposer acts as MEMS carrier or lid and therefore is part of the final packaged component after dicing. AuSn rings have been chosen for process compatibility with the MEMS and ensure the hermeticity of the components after vacuum sealing. Evaluation of the bond process is carried out using XRay imaging microscopy, analysis of cross sections and the final package resistance is evaluated using shear testing. The thickness of the chip-scale packaged MEMS is smaller than 500 µm and a yield of vacuum sealing of around 80% was obtained in first evaluation on 200 mm wafer scale

AB - Results of wafer level packaging for micro-electro-mechanical systems based on low temperature melting metallurgy are going to be presented. The MEMS are packaged under vacuum with internal pressure in the range of 1 mbar after sealing. Through Silicon Vias in a silicon interposer allow the feeding of the electrical contacts to the package outside. The thin silicon interposer acts as MEMS carrier or lid and therefore is part of the final packaged component after dicing. AuSn rings have been chosen for process compatibility with the MEMS and ensure the hermeticity of the components after vacuum sealing. Evaluation of the bond process is carried out using XRay imaging microscopy, analysis of cross sections and the final package resistance is evaluated using shear testing. The thickness of the chip-scale packaged MEMS is smaller than 500 µm and a yield of vacuum sealing of around 80% was obtained in first evaluation on 200 mm wafer scale

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Manier C-A, Zoschke K, Oppermann H, Ruffieux D, Dalla Piazza S, Suni T et al. Vacuum packaging at wafer level for MEMS using gold-tin metallurgy. In 2013 European Microelectronics Packaging Conference (EMPC). IEEE Institute of Electrical and Electronic Engineers . 2013. 6698698