Verification of FPGA application design by model checking

Research output: Contribution to conferenceOther conference contributionScientific

Original languageEnglish
Publication statusPublished - 2016
MoE publication typeNot Eligible
Event9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants - Lyon, France
Duration: 3 Oct 20166 Oct 2016

Workshop

Workshop9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants
CountryFrance
CityLyon
Period3/10/166/10/16

Keywords

  • model checking
  • FPGA
  • PLD
  • formal verification
  • nuclear power

Cite this

Pakonen, A. (2016). Verification of FPGA application design by model checking. 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants, Lyon, France. http://www.vtt.fi/inf/julkaisut/muut/2016/OA-Verification-of-FPGA-Application%20.pdf