Verification of FPGA application design by model checking

Research output: Contribution to conferenceOther conference contributionScientific

Original languageEnglish
Publication statusPublished - 2016
Event9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants - Lyon, France
Duration: 3 Oct 20166 Oct 2016

Workshop

Workshop9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants
CountryFrance
CityLyon
Period3/10/166/10/16

Keywords

  • model checking
  • FPGA
  • PLD
  • formal verification
  • nuclear power

Cite this

Pakonen, A. (2016). Verification of FPGA application design by model checking. 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants, Lyon, France.
Pakonen, Antti. / Verification of FPGA application design by model checking. 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants, Lyon, France.
@conference{6056d15bd7ef453e95ac5893d37895f3,
title = "Verification of FPGA application design by model checking",
keywords = "model checking, FPGA, PLD, formal verification, nuclear power",
author = "Antti Pakonen",
note = "Project code: 108550 ; 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants ; Conference date: 03-10-2016 Through 06-10-2016",
year = "2016",
language = "English",

}

Pakonen, A 2016, 'Verification of FPGA application design by model checking' 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants, Lyon, France, 3/10/16 - 6/10/16, .

Verification of FPGA application design by model checking. / Pakonen, Antti.

2016. 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants, Lyon, France.

Research output: Contribution to conferenceOther conference contributionScientific

TY - CONF

T1 - Verification of FPGA application design by model checking

AU - Pakonen, Antti

N1 - Project code: 108550

PY - 2016

Y1 - 2016

KW - model checking

KW - FPGA

KW - PLD

KW - formal verification

KW - nuclear power

M3 - Other conference contribution

ER -

Pakonen A. Verification of FPGA application design by model checking. 2016. 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants, Lyon, France.