Verification of FPGA application design by model checking

Antti Pakonen

Verification of FPGA application design by model checking

BA1621 AI-aided systems engineering

Research output: Contribution to conference › Other conference contribution › Scientific

Original language	English
Publication status	Published - 2016
MoE publication type	Not Eligible
Event	9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants - Lyon, France Duration: 3 Oct 2016 → 6 Oct 2016

Workshop

Workshop	9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants
Country	France
City	Lyon
Period	3/10/16 → 6/10/16

Keywords

model checking
FPGA
PLD
formal verification
nuclear power

Access to Document

http://www.vtt.fi/inf/julkaisut/muut/2016/OA-Verification-of-FPGA-Application%20.pdf

Cite this

@conference{6056d15bd7ef453e95ac5893d37895f3,

title = "Verification of FPGA application design by model checking",

keywords = "model checking, FPGA, PLD, formal verification, nuclear power",

author = "Antti Pakonen",

note = "Project code: 108550 ; 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants ; Conference date: 03-10-2016 Through 06-10-2016",

year = "2016",

language = "English",

}

TY - CONF

T1 - Verification of FPGA application design by model checking

AU - Pakonen, Antti

N1 - Project code: 108550

PY - 2016

Y1 - 2016

KW - model checking

KW - FPGA

KW - PLD

KW - formal verification

KW - nuclear power

M3 - Other conference contribution

T2 - 9th International Workshop on the Application of Field Programmable Gate Arrays in Nuclear Power Plants

Y2 - 3 October 2016 through 6 October 2016

ER -