This work studies the system-level design methodologies of large System-on-Chips. As semiconductor technologies advance, the complexity of system-on-chips grows rapidly, causing problems in every phase of design flow. This work presents a system-level design methodology for early estimation of the quality and performance of designed architecture. As a case example, a system-on-chip designed around four DSP processor cores was used. This case example is targeted for telecommunications and multimedia products. It was designed so that it can be configured for different kinds of digital signal processing workloads. Two basic types of digital signal processing were identified: stream-based and block-based signal processing. As an example application of block-based processing, MPEG-2 video decoding was used; as an example of stream-based processing, a subset of a HiperLAN/2 wireless local area network modem was used. A transaction-level model of the system-on-chip was designed and workload models of applications were designed using SystemC 2.0 language and the Synopsys CoCentric System Studio tool. According to the simulations, the designed configurable shared memory system increases performance over traditional bus-based shared memory systems. The transaction-level modeling proved to be a fast and easy method of gathering simulation-based information about the performance characteristics of an architecture.
|Place of Publication||Oulu|
|Publication status||Published - 2002|
|MoE publication type||G2 Master's thesis, polytechnic Master's thesis|
- system-level design
- configurable shared memory
- transaction-level modeling