Virtual component-based multiprocessor DSP architecture

Master's thesis

Antti Pelkonen

Research output: ThesisMaster's thesisTheses

Abstract

This work studies the system-level design methodologies of large System-on-Chips. As semiconductor technologies advance, the complexity of system-on-chips grows rapidly, causing problems in every phase of design flow. This work presents a system-level design methodology for early estimation of the quality and performance of designed architecture. As a case example, a system-on-chip designed around four DSP processor cores was used. This case example is targeted for telecommunications and multimedia products. It was designed so that it can be configured for different kinds of digital signal processing workloads. Two basic types of digital signal processing were identified: stream-based and block-based signal processing. As an example application of block-based processing, MPEG-2 video decoding was used; as an example of stream-based processing, a subset of a HiperLAN/2 wireless local area network modem was used. A transaction-level model of the system-on-chip was designed and workload models of applications were designed using SystemC 2.0 language and the Synopsys CoCentric System Studio tool. According to the simulations, the designed configurable shared memory system increases performance over traditional bus-based shared memory systems. The transaction-level modeling proved to be a fast and easy method of gathering simulation-based information about the performance characteristics of an architecture.
Original languageEnglish
QualificationMaster Degree
Awarding Institution
  • University of Oulu
Place of PublicationOulu
Publisher
Publication statusPublished - 2002
MoE publication typeG2 Master's thesis, polytechnic Master's thesis

Fingerprint

Digital signal processing
Data storage equipment
Studios
Modems
Processing
Wireless local area networks (WLAN)
Telecommunication
Decoding
Signal processing
Computer systems
Semiconductor materials
System-on-chip

Keywords

  • system-on-chip
  • system-level design
  • configurable shared memory
  • transaction-level modeling
  • SystemC

Cite this

Pelkonen, A. (2002). Virtual component-based multiprocessor DSP architecture: Master's thesis. Oulu: University of Oulu.
Pelkonen, Antti. / Virtual component-based multiprocessor DSP architecture : Master's thesis. Oulu : University of Oulu, 2002. 63 p.
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abstract = "This work studies the system-level design methodologies of large System-on-Chips. As semiconductor technologies advance, the complexity of system-on-chips grows rapidly, causing problems in every phase of design flow. This work presents a system-level design methodology for early estimation of the quality and performance of designed architecture. As a case example, a system-on-chip designed around four DSP processor cores was used. This case example is targeted for telecommunications and multimedia products. It was designed so that it can be configured for different kinds of digital signal processing workloads. Two basic types of digital signal processing were identified: stream-based and block-based signal processing. As an example application of block-based processing, MPEG-2 video decoding was used; as an example of stream-based processing, a subset of a HiperLAN/2 wireless local area network modem was used. A transaction-level model of the system-on-chip was designed and workload models of applications were designed using SystemC 2.0 language and the Synopsys CoCentric System Studio tool. According to the simulations, the designed configurable shared memory system increases performance over traditional bus-based shared memory systems. The transaction-level modeling proved to be a fast and easy method of gathering simulation-based information about the performance characteristics of an architecture.",
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Pelkonen, A 2002, 'Virtual component-based multiprocessor DSP architecture: Master's thesis', Master Degree, University of Oulu, Oulu.

Virtual component-based multiprocessor DSP architecture : Master's thesis. / Pelkonen, Antti.

Oulu : University of Oulu, 2002. 63 p.

Research output: ThesisMaster's thesisTheses

TY - THES

T1 - Virtual component-based multiprocessor DSP architecture

T2 - Master's thesis

AU - Pelkonen, Antti

N1 - CA: ELE OH: diplomityö Oulun yliopisto, Sähkötekniikan osasto

PY - 2002

Y1 - 2002

N2 - This work studies the system-level design methodologies of large System-on-Chips. As semiconductor technologies advance, the complexity of system-on-chips grows rapidly, causing problems in every phase of design flow. This work presents a system-level design methodology for early estimation of the quality and performance of designed architecture. As a case example, a system-on-chip designed around four DSP processor cores was used. This case example is targeted for telecommunications and multimedia products. It was designed so that it can be configured for different kinds of digital signal processing workloads. Two basic types of digital signal processing were identified: stream-based and block-based signal processing. As an example application of block-based processing, MPEG-2 video decoding was used; as an example of stream-based processing, a subset of a HiperLAN/2 wireless local area network modem was used. A transaction-level model of the system-on-chip was designed and workload models of applications were designed using SystemC 2.0 language and the Synopsys CoCentric System Studio tool. According to the simulations, the designed configurable shared memory system increases performance over traditional bus-based shared memory systems. The transaction-level modeling proved to be a fast and easy method of gathering simulation-based information about the performance characteristics of an architecture.

AB - This work studies the system-level design methodologies of large System-on-Chips. As semiconductor technologies advance, the complexity of system-on-chips grows rapidly, causing problems in every phase of design flow. This work presents a system-level design methodology for early estimation of the quality and performance of designed architecture. As a case example, a system-on-chip designed around four DSP processor cores was used. This case example is targeted for telecommunications and multimedia products. It was designed so that it can be configured for different kinds of digital signal processing workloads. Two basic types of digital signal processing were identified: stream-based and block-based signal processing. As an example application of block-based processing, MPEG-2 video decoding was used; as an example of stream-based processing, a subset of a HiperLAN/2 wireless local area network modem was used. A transaction-level model of the system-on-chip was designed and workload models of applications were designed using SystemC 2.0 language and the Synopsys CoCentric System Studio tool. According to the simulations, the designed configurable shared memory system increases performance over traditional bus-based shared memory systems. The transaction-level modeling proved to be a fast and easy method of gathering simulation-based information about the performance characteristics of an architecture.

KW - system-on-chip

KW - system-level design

KW - configurable shared memory

KW - transaction-level modeling

KW - SystemC

M3 - Master's thesis

PB - University of Oulu

CY - Oulu

ER -

Pelkonen A. Virtual component-based multiprocessor DSP architecture: Master's thesis. Oulu: University of Oulu, 2002. 63 p.