Designing a complex system-on-a-chip poses many challenges. Network on chip (NOC) is an architectural template, which can help meet many of these challenges and enable fast time to market for new products. NOC provides vertical integration of physical and architectural levels in system design, which helps in reuse at various levels of design. A NOC template consists of continuous areas called regions. A region of NOC will be composed of computing and storage resources connected by a switching fabric for message based communication. While providing standardized way for communication among resources, generic NOC region architecture does not provide efficient access for shared data to computing resources involved in parallel processing in a computation intensive algorithm. In this paper, we propose hardware architecture for implementing distributed shared memory in a NOC region, which solves the above problem. Through an analytical analysis, we show that the proposed hardware structure has much higher performance than the baseline NOC architecture.
|Title of host publication||Proceedings of the 2001 19th Norchip Conference|
|Publication status||Published - 2001|
|MoE publication type||A4 Article in a conference publication|
|Event||19th IEEE Norchip Conference, NORCHIP 2001 - Kista, Sweden|
Duration: 12 Nov 2001 → 13 Nov 2001
|Conference||19th IEEE Norchip Conference, NORCHIP 2001|
|Period||12/11/01 → 13/11/01|