Void formation over limiting current density and impurity analysis of TSV fabricated by constant-current pulse-reverse modulation

Microstructure and impurity incorporation are important in through-silicon via (TSV) fabrication due to their relationships to reliability and integrity of the fabricated Microsystems. In this paper, the analysis of microstructure and impurity incorporation of through-silicon vias of different diameters ranging from 60 to 150 μm fabricated using different pulse-reverse current modulations are reported. It was observed that at the low current density of 20 mA/cm2, all the through-holes with different diameters are filled with copper without voids and pores. But at the higher current density of 30 mA/cm2, the pillars with diameters of 100 μm or larger tend to have void at the middle portion. Preferential deposition at the perimeter of TSV during plating causes the variation of grain sizes in TSV and accelerated deposition. Smaller grain sizes are observed when the void at the core of the TSV begins to form. Impurity analysis using time-of-flight secondary ion mass spectroscopy (ToF-SIMS) shows the significant difference in impurity level in smaller TSV. Previously observed nanotwins in TSV is partly due to high impurity incorporation rate in the high-aspect ratio trenches. TSVs with larger diameter show no such tendencies which confirm the constant hardness along the length of TSV in previous studies [1]. The localized impurity spots are found in SIMS analysis, which are due to larger grain sizes and segregation of impurity species to the grain boundaries area.