Wafer level package for device

Jae-Wung Lee

Wafer level package for device

Jae-Wung Lee (Inventor)

BA6215 Photonics and superconductive electronics

Research output: Patent › Patent

Abstract

According to an example aspect of the present invention, there is provided a wafer level package (100) for a device, the package (100) comprising a first substrate (102) and a second substrate (103), at least one insulating stand-off structure (104) between the first substrate (102) and the second substrate (103), a bonding layer (108) on the at least one stand-off structure (104), and a first lateral electrical connection line (109) on a surface of the first substrate (102) and a second lateral electrical connection line (110) on a surface the second substrate (103), wherein electrical connection is formed between the first lateral electrical connection line (109) and the second lateral connection line (110) via the bonding layer (108) of the at least one stand-off structure (104).

Patent family as of 21.7.2026
EP4214150 A1, EP4214150 B1, EP4214150 C0, FI20205914 A, JP2023544110 T2, JP7705928 B2, US2023382721 AA, WO22058659 A1

Original language	English
Patent number	EP4214150 B1
IPC	B81B7/00
Priority date	21/09/20
Filing date	20/09/21
Publication status	Published - 8 Apr 2026
MoE publication type	H1 Granted patent

Cite this

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title = "Wafer level package for device",

abstract = "According to an example aspect of the present invention, there is provided a wafer level package (100) for a device, the package (100) comprising a first substrate (102) and a second substrate (103), at least one insulating stand-off structure (104) between the first substrate (102) and the second substrate (103), a bonding layer (108) on the at least one stand-off structure (104), and a first lateral electrical connection line (109) on a surface of the first substrate (102) and a second lateral electrical connection line (110) on a surface the second substrate (103), wherein electrical connection is formed between the first lateral electrical connection line (109) and the second lateral connection line (110) via the bonding layer (108) of the at least one stand-off structure (104). Patent family as of 21.7.2026 EP4214150 A1, EP4214150 B1, EP4214150 C0, FI20205914 A, JP2023544110 T2, JP7705928 B2, US2023382721 AA, WO22058659 A1",

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T1 - Wafer level package for device

AU - Lee, Jae-Wung

PY - 2026/4/8

Y1 - 2026/4/8

N2 - According to an example aspect of the present invention, there is provided a wafer level package (100) for a device, the package (100) comprising a first substrate (102) and a second substrate (103), at least one insulating stand-off structure (104) between the first substrate (102) and the second substrate (103), a bonding layer (108) on the at least one stand-off structure (104), and a first lateral electrical connection line (109) on a surface of the first substrate (102) and a second lateral electrical connection line (110) on a surface the second substrate (103), wherein electrical connection is formed between the first lateral electrical connection line (109) and the second lateral connection line (110) via the bonding layer (108) of the at least one stand-off structure (104). Patent family as of 21.7.2026 EP4214150 A1, EP4214150 B1, EP4214150 C0, FI20205914 A, JP2023544110 T2, JP7705928 B2, US2023382721 AA, WO22058659 A1

AB - According to an example aspect of the present invention, there is provided a wafer level package (100) for a device, the package (100) comprising a first substrate (102) and a second substrate (103), at least one insulating stand-off structure (104) between the first substrate (102) and the second substrate (103), a bonding layer (108) on the at least one stand-off structure (104), and a first lateral electrical connection line (109) on a surface of the first substrate (102) and a second lateral electrical connection line (110) on a surface the second substrate (103), wherein electrical connection is formed between the first lateral electrical connection line (109) and the second lateral connection line (110) via the bonding layer (108) of the at least one stand-off structure (104). Patent family as of 21.7.2026 EP4214150 A1, EP4214150 B1, EP4214150 C0, FI20205914 A, JP2023544110 T2, JP7705928 B2, US2023382721 AA, WO22058659 A1

UR - https://fi.espacenet.com/publicationDetails/biblio?II=0&ND=3&adjacent=true&locale=fi_FI&FT=D&date=20231130&CC=US&NR=2023382721A1&KC=A1

M3 - Patent

M1 - EP4214150 B1

Y2 - 2021/09/20

ER -

Wafer level package for device

Abstract

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