Abstract
According to an example aspect of the present invention, there is provided a wafer-level package (1), comprising a top substrate (10) and a bottom substrate (30), wherein the top substrate (10) comprises a recess (12) on a side of the top substrate (10) which is towards the bottom substrate (30) and the bottom substrate (30) comprises a recess (32) on a side of the bottom substrate (30) which is towards the top substrate (10), wherein the recess (12) of the top substrate (10) and the recess (32) of the bottom substrate (30) are arranged to form a waveguide (5) within the wafer-level package (1) and a middle substrate (20) arranged to couple an integrated circuit (24) of the wafer-level package (1) to the waveguide (5), wherein the middle substrate (20) is in between the top substrate (10) and the bottom substrate (30) and the middle substrate (20) comprises a probe (21), wherein the probe (21) extends to the waveguide (5) and the probe (21) is arranged to couple a signal coming from the integrated circuit (24) to the waveguide (5), or to couple a signal coming from the waveguide (5) to the integrated circuit (24).
Patent family as of 21.7.2026
EP4229714 A1, FI20206003 A, US12575424 BB, US2023387045 AA, WO22079348 A1
Patent family as of 21.7.2026
EP4229714 A1, FI20206003 A, US12575424 BB, US2023387045 AA, WO22079348 A1
| Original language | English |
|---|---|
| Patent number | US12575424 B2 |
| IPC | H01L23/00 |
| Priority date | 13/10/20 |
| Filing date | 8/10/21 |
| Publication status | Published - 10 Mar 2026 |
| MoE publication type | H1 Granted patent |
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