Wafer level packaging for hermetical encapsulation of MEMS resonators

C.-A. Manier, K. Zoschke, H. Oppermann, D. Ruffieux, Silvio Dalla Piazza, Tommi Suni, J. Dekker, G. Allegato

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

6 Citations (Scopus)

Abstract

This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy have been considered for process compatibility with MEMS and provide the hermetical sealing of the components after vacuum encapsulation. Different packaging processes were tested and are here succinctly presented for established quartz crystals as well as for emerging Silicon Resonators (SiRes). First investigations on if, and possibly how, wafer dicing affects the packaged components were performed. A yield of 80% could be achieved in wafer level packaging of quartz crystal resonators at 8" wafer scale first step towards an ongoing 3D integration with CMOS. © 2015 IEEE.
Original languageEnglish
Title of host publicationDesign, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on
PublisherInstitute of Electrical and Electronic Engineers IEEE
Pages1-6
ISBN (Electronic)978-1-4799-8625-5
ISBN (Print)978-1-4799-8627-9
DOIs
Publication statusPublished - 20 Jul 2015
MoE publication typeA4 Article in a conference publication
Event17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015 - Montpellier, France
Duration: 27 Apr 201530 Apr 2015
Conference number: 17

Other

Other17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015
Abbreviated titleDTIP 2015
CountryFrance
CityMontpellier
Period27/04/1530/04/15

Fingerprint

Encapsulation
MEMS
Resonators
Wafer bonding
Packaging
Quartz
Vacuum
Crystal resonators
Silicon
Metallurgy
Seals
Fabrication
Crystals

Keywords

  • Au/Sn
  • interposer
  • MEMS resonator
  • sealing
  • TSV
  • vacuum
  • WLP

Cite this

Manier, C-A., Zoschke, K., Oppermann, H., Ruffieux, D., Dalla Piazza, S., Suni, T., ... Allegato, G. (2015). Wafer level packaging for hermetical encapsulation of MEMS resonators. In Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on (pp. 1-6). Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/DTIP.2015.7161027
Manier, C.-A. ; Zoschke, K. ; Oppermann, H. ; Ruffieux, D. ; Dalla Piazza, Silvio ; Suni, Tommi ; Dekker, J. ; Allegato, G. / Wafer level packaging for hermetical encapsulation of MEMS resonators. Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on. Institute of Electrical and Electronic Engineers IEEE, 2015. pp. 1-6
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Manier, C-A, Zoschke, K, Oppermann, H, Ruffieux, D, Dalla Piazza, S, Suni, T, Dekker, J & Allegato, G 2015, Wafer level packaging for hermetical encapsulation of MEMS resonators. in Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on. Institute of Electrical and Electronic Engineers IEEE, pp. 1-6, 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015, Montpellier, France, 27/04/15. https://doi.org/10.1109/DTIP.2015.7161027

Wafer level packaging for hermetical encapsulation of MEMS resonators. / Manier, C.-A.; Zoschke, K.; Oppermann, H.; Ruffieux, D.; Dalla Piazza, Silvio; Suni, Tommi; Dekker, J.; Allegato, G.

Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on. Institute of Electrical and Electronic Engineers IEEE, 2015. p. 1-6.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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N2 - This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy have been considered for process compatibility with MEMS and provide the hermetical sealing of the components after vacuum encapsulation. Different packaging processes were tested and are here succinctly presented for established quartz crystals as well as for emerging Silicon Resonators (SiRes). First investigations on if, and possibly how, wafer dicing affects the packaged components were performed. A yield of 80% could be achieved in wafer level packaging of quartz crystal resonators at 8" wafer scale first step towards an ongoing 3D integration with CMOS. © 2015 IEEE.

AB - This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy have been considered for process compatibility with MEMS and provide the hermetical sealing of the components after vacuum encapsulation. Different packaging processes were tested and are here succinctly presented for established quartz crystals as well as for emerging Silicon Resonators (SiRes). First investigations on if, and possibly how, wafer dicing affects the packaged components were performed. A yield of 80% could be achieved in wafer level packaging of quartz crystal resonators at 8" wafer scale first step towards an ongoing 3D integration with CMOS. © 2015 IEEE.

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Manier C-A, Zoschke K, Oppermann H, Ruffieux D, Dalla Piazza S, Suni T et al. Wafer level packaging for hermetical encapsulation of MEMS resonators. In Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on. Institute of Electrical and Electronic Engineers IEEE. 2015. p. 1-6 https://doi.org/10.1109/DTIP.2015.7161027