Abstract
This paper will present wafer level packaging approaches
and results for MEMS encapsulation and integration
applied to resonators. The core technologies involve
interposer fabrication with Through-Silicon Vias (TSV),
temporary wafer bonding for thin wafer handling and wafer
bonding for metallic sealing under vacuum and for
formation of electrical interconnects. Seal rings based
on AuSn metallurgy have been considered for process
compatibility with MEMS and provide the hermetical
sealing of the components after vacuum encapsulation.
Different packaging processes were tested and are here
succinctly presented for established quartz crystals as
well as for emerging Silicon Resonators (SiRes). First
investigations on if, and possibly how, wafer dicing
affects the packaged components were performed. A yield
of 80% could be achieved in wafer level packaging of
quartz crystal resonators at 8" wafer scale first step
towards an ongoing 3D integration with CMOS. © 2015 IEEE.
Original language | English |
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Title of host publication | 2015 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP) |
Publisher | IEEE Institute of Electrical and Electronic Engineers |
Pages | 1-6 |
ISBN (Electronic) | 978-1-4799-8625-5 |
ISBN (Print) | 978-1-4799-8627-9 |
DOIs | |
Publication status | Published - 20 Jul 2015 |
MoE publication type | A4 Article in a conference publication |
Event | 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015 - Montpellier, France Duration: 27 Apr 2015 → 30 Apr 2015 Conference number: 17 |
Other
Other | 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015 |
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Abbreviated title | DTIP 2015 |
Country/Territory | France |
City | Montpellier |
Period | 27/04/15 → 30/04/15 |
Keywords
- Au/Sn
- interposer
- MEMS resonator
- sealing
- TSV
- vacuum
- WLP