Wafer level packaging for hermetical encapsulation of MEMS resonators

C.-A. Manier; K. Zoschke; H. Oppermann; D. Ruffieux; Silvio  Dalla Piazza; Tommi Suni; J. Dekker; G. Allegato

doi:10.1109/DTIP.2015.7161027

Wafer level packaging for hermetical encapsulation of MEMS resonators

C.-A. Manier, K. Zoschke, H. Oppermann, D. Ruffieux, Silvio Dalla Piazza, Tommi Suni, J. Dekker, G. Allegato

VTT Technical Research Centre of Finland

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

6 Citations (Scopus)

Abstract

This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy have been considered for process compatibility with MEMS and provide the hermetical sealing of the components after vacuum encapsulation. Different packaging processes were tested and are here succinctly presented for established quartz crystals as well as for emerging Silicon Resonators (SiRes). First investigations on if, and possibly how, wafer dicing affects the packaged components were performed. A yield of 80% could be achieved in wafer level packaging of quartz crystal resonators at 8" wafer scale first step towards an ongoing 3D integration with CMOS. © 2015 IEEE.

Original language	English
Title of host publication	Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	1-6
ISBN (Electronic)	978-1-4799-8625-5
ISBN (Print)	978-1-4799-8627-9
DOIs	https://doi.org/10.1109/DTIP.2015.7161027
Publication status	Published - 20 Jul 2015
MoE publication type	A4 Article in a conference publication
Event	17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015 - Montpellier, France Duration: 27 Apr 2015 → 30 Apr 2015 Conference number: 17

Other

Other	17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015
Abbreviated title	DTIP 2015
Country	France
City	Montpellier
Period	27/04/15 → 30/04/15

Keywords

Au/Sn
interposer
MEMS resonator
sealing
TSV
vacuum
WLP

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Manier, C-A., Zoschke, K., Oppermann, H., Ruffieux, D., Dalla Piazza, S., Suni, T., Dekker, J., & Allegato, G. (2015). Wafer level packaging for hermetical encapsulation of MEMS resonators. In Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on (pp. 1-6). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/DTIP.2015.7161027

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abstract = "This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy have been considered for process compatibility with MEMS and provide the hermetical sealing of the components after vacuum encapsulation. Different packaging processes were tested and are here succinctly presented for established quartz crystals as well as for emerging Silicon Resonators (SiRes). First investigations on if, and possibly how, wafer dicing affects the packaged components were performed. A yield of 80% could be achieved in wafer level packaging of quartz crystal resonators at 8{"} wafer scale first step towards an ongoing 3D integration with CMOS. {\textcopyright} 2015 IEEE.",

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author = "C.-A. Manier and K. Zoschke and H. Oppermann and D. Ruffieux and {Dalla Piazza}, Silvio and Tommi Suni and J. Dekker and G. Allegato",

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Manier, C-A, Zoschke, K, Oppermann, H, Ruffieux, D, Dalla Piazza, S, Suni, T, Dekker, J & Allegato, G 2015, Wafer level packaging for hermetical encapsulation of MEMS resonators. in Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on. IEEE Institute of Electrical and Electronic Engineers, pp. 1-6, 17th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2015, Montpellier, France, 27/04/15. https://doi.org/10.1109/DTIP.2015.7161027

Wafer level packaging for hermetical encapsulation of MEMS resonators. / Manier, C.-A.; Zoschke, K.; Oppermann, H.; Ruffieux, D.; Dalla Piazza, Silvio; Suni, Tommi; Dekker, J.; Allegato, G.

Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on. IEEE Institute of Electrical and Electronic Engineers, 2015. p. 1-6.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

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AU - Manier, C.-A.

AU - Zoschke, K.

AU - Oppermann, H.

AU - Ruffieux, D.

AU - Dalla Piazza, Silvio

AU - Suni, Tommi

AU - Dekker, J.

AU - Allegato, G.

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N2 - This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy have been considered for process compatibility with MEMS and provide the hermetical sealing of the components after vacuum encapsulation. Different packaging processes were tested and are here succinctly presented for established quartz crystals as well as for emerging Silicon Resonators (SiRes). First investigations on if, and possibly how, wafer dicing affects the packaged components were performed. A yield of 80% could be achieved in wafer level packaging of quartz crystal resonators at 8" wafer scale first step towards an ongoing 3D integration with CMOS. © 2015 IEEE.

AB - This paper will present wafer level packaging approaches and results for MEMS encapsulation and integration applied to resonators. The core technologies involve interposer fabrication with Through-Silicon Vias (TSV), temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and for formation of electrical interconnects. Seal rings based on AuSn metallurgy have been considered for process compatibility with MEMS and provide the hermetical sealing of the components after vacuum encapsulation. Different packaging processes were tested and are here succinctly presented for established quartz crystals as well as for emerging Silicon Resonators (SiRes). First investigations on if, and possibly how, wafer dicing affects the packaged components were performed. A yield of 80% could be achieved in wafer level packaging of quartz crystal resonators at 8" wafer scale first step towards an ongoing 3D integration with CMOS. © 2015 IEEE.

KW - Au/Sn

KW - interposer

KW - MEMS resonator

KW - sealing

KW - TSV

KW - vacuum

KW - WLP

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M3 - Conference article in proceedings

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BT - Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2015 Symposium on

PB - IEEE Institute of Electrical and Electronic Engineers

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Y2 - 27 April 2015 through 30 April 2015

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