Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

Charles-Alix Manier, Kai Zoschke, Martin Wilke, Hermann Oppermann, David Ruffieux, Silvio Dalla Piazza, Tommi Suni, James Dekker, Giorgio Allegato, Klaus-Dieter Lang

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

3 Citations (Scopus)

Abstract

The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. The packaging of the timing module consists in the integration of an ASIC together with a Quartz-based or Twin-Silicon resonator MEMS which require to be hermetically sealed under vacuum for proper function. The 3D-integration enables a significant miniaturization of the complete system. Subsequently a BAW (Bulk Acoustic Wave) resonator can be further associated over the quartz resonator to form a MEMS-based freely programmable oscillator for stable clock generation, covering a large frequency range between 1 and 50 MHz. The principal fabrication processes include the implementation of Through-Silicon Vias (TSV) in active CMOS wafers, temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and formation of electrical interconnects. The components were packaged by chip to wafer assembly onto active CMOS wafers with TSVs and subsequent wafer to wafer bonding with a corresponding cavity cap wafer for vacuum encapsulation. All processes have been developed and performed at 200 mm industrial wafer scale.
Original languageEnglish
Title of host publicationDesign, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on
PublisherInstitute of Electrical and Electronic Engineers IEEE
Pages1-6
ISBN (Electronic)978-1-5090-1457-6, 978-1-5090-1458-3
ISBN (Print)978-1-5090-1391-3
DOIs
Publication statusPublished - 18 Jul 2016
MoE publication typeA4 Article in a conference publication
Event18th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2016 - Budapest, Hungary
Duration: 30 May 20162 Jun 2016
Conference number: 18

Conference

Conference18th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2016
Abbreviated titleDTIP 2016
CountryHungary
CityBudapest
Period30/05/162/06/16

Fingerprint

packaging
microelectromechanical systems
CMOS
time measurement
wafers
fabrication
resonators
vacuum
quartz
modules
application specific integrated circuits
sealing
miniaturization
silicon
caps
clocks
coverings
assembly
frequency ranges
chips

Keywords

  • ASIC
  • Au/Sn
  • bonding
  • CMOS
  • encapsulation
  • interposer
  • MEMS resonator
  • Packaging
  • sealing
  • TSV
  • vacuum
  • via last
  • wafer
  • WLP

Cite this

Manier, C-A., Zoschke, K., Wilke, M., Oppermann, H., Ruffieux, D., Dalla Piazza, S., ... Lang, K-D. (2016). Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems. In Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on (pp. 1-6). Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/DTIP.2016.7514832
Manier, Charles-Alix ; Zoschke, Kai ; Wilke, Martin ; Oppermann, Hermann ; Ruffieux, David ; Dalla Piazza, Silvio ; Suni, Tommi ; Dekker, James ; Allegato, Giorgio ; Lang, Klaus-Dieter. / Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems. Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on. Institute of Electrical and Electronic Engineers IEEE, 2016. pp. 1-6
@inproceedings{5878870602454ce2855c8c895846cc70,
title = "Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems",
abstract = "The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. The packaging of the timing module consists in the integration of an ASIC together with a Quartz-based or Twin-Silicon resonator MEMS which require to be hermetically sealed under vacuum for proper function. The 3D-integration enables a significant miniaturization of the complete system. Subsequently a BAW (Bulk Acoustic Wave) resonator can be further associated over the quartz resonator to form a MEMS-based freely programmable oscillator for stable clock generation, covering a large frequency range between 1 and 50 MHz. The principal fabrication processes include the implementation of Through-Silicon Vias (TSV) in active CMOS wafers, temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and formation of electrical interconnects. The components were packaged by chip to wafer assembly onto active CMOS wafers with TSVs and subsequent wafer to wafer bonding with a corresponding cavity cap wafer for vacuum encapsulation. All processes have been developed and performed at 200 mm industrial wafer scale.",
keywords = "ASIC, Au/Sn, bonding, CMOS, encapsulation, interposer, MEMS resonator, Packaging, sealing, TSV, vacuum, via last, wafer, WLP",
author = "Charles-Alix Manier and Kai Zoschke and Martin Wilke and Hermann Oppermann and David Ruffieux and {Dalla Piazza}, Silvio and Tommi Suni and James Dekker and Giorgio Allegato and Klaus-Dieter Lang",
year = "2016",
month = "7",
day = "18",
doi = "10.1109/DTIP.2016.7514832",
language = "English",
isbn = "978-1-5090-1391-3",
pages = "1--6",
booktitle = "Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on",
publisher = "Institute of Electrical and Electronic Engineers IEEE",
address = "United States",

}

Manier, C-A, Zoschke, K, Wilke, M, Oppermann, H, Ruffieux, D, Dalla Piazza, S, Suni, T, Dekker, J, Allegato, G & Lang, K-D 2016, Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems. in Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on. Institute of Electrical and Electronic Engineers IEEE, pp. 1-6, 18th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2016, Budapest, Hungary, 30/05/16. https://doi.org/10.1109/DTIP.2016.7514832

Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems. / Manier, Charles-Alix; Zoschke, Kai; Wilke, Martin; Oppermann, Hermann; Ruffieux, David; Dalla Piazza, Silvio; Suni, Tommi; Dekker, James; Allegato, Giorgio; Lang, Klaus-Dieter.

Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on. Institute of Electrical and Electronic Engineers IEEE, 2016. p. 1-6.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

TY - GEN

T1 - Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

AU - Manier, Charles-Alix

AU - Zoschke, Kai

AU - Wilke, Martin

AU - Oppermann, Hermann

AU - Ruffieux, David

AU - Dalla Piazza, Silvio

AU - Suni, Tommi

AU - Dekker, James

AU - Allegato, Giorgio

AU - Lang, Klaus-Dieter

PY - 2016/7/18

Y1 - 2016/7/18

N2 - The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. The packaging of the timing module consists in the integration of an ASIC together with a Quartz-based or Twin-Silicon resonator MEMS which require to be hermetically sealed under vacuum for proper function. The 3D-integration enables a significant miniaturization of the complete system. Subsequently a BAW (Bulk Acoustic Wave) resonator can be further associated over the quartz resonator to form a MEMS-based freely programmable oscillator for stable clock generation, covering a large frequency range between 1 and 50 MHz. The principal fabrication processes include the implementation of Through-Silicon Vias (TSV) in active CMOS wafers, temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and formation of electrical interconnects. The components were packaged by chip to wafer assembly onto active CMOS wafers with TSVs and subsequent wafer to wafer bonding with a corresponding cavity cap wafer for vacuum encapsulation. All processes have been developed and performed at 200 mm industrial wafer scale.

AB - The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. The packaging of the timing module consists in the integration of an ASIC together with a Quartz-based or Twin-Silicon resonator MEMS which require to be hermetically sealed under vacuum for proper function. The 3D-integration enables a significant miniaturization of the complete system. Subsequently a BAW (Bulk Acoustic Wave) resonator can be further associated over the quartz resonator to form a MEMS-based freely programmable oscillator for stable clock generation, covering a large frequency range between 1 and 50 MHz. The principal fabrication processes include the implementation of Through-Silicon Vias (TSV) in active CMOS wafers, temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and formation of electrical interconnects. The components were packaged by chip to wafer assembly onto active CMOS wafers with TSVs and subsequent wafer to wafer bonding with a corresponding cavity cap wafer for vacuum encapsulation. All processes have been developed and performed at 200 mm industrial wafer scale.

KW - ASIC

KW - Au/Sn

KW - bonding

KW - CMOS

KW - encapsulation

KW - interposer

KW - MEMS resonator

KW - Packaging

KW - sealing

KW - TSV

KW - vacuum

KW - via last

KW - wafer

KW - WLP

U2 - 10.1109/DTIP.2016.7514832

DO - 10.1109/DTIP.2016.7514832

M3 - Conference article in proceedings

SN - 978-1-5090-1391-3

SP - 1

EP - 6

BT - Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on

PB - Institute of Electrical and Electronic Engineers IEEE

ER -

Manier C-A, Zoschke K, Wilke M, Oppermann H, Ruffieux D, Dalla Piazza S et al. Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems. In Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on. Institute of Electrical and Electronic Engineers IEEE. 2016. p. 1-6 https://doi.org/10.1109/DTIP.2016.7514832