Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

Charles-Alix Manier, Kai Zoschke, Martin Wilke, Hermann Oppermann, David Ruffieux, Silvio Dalla Piazza, Tommi Suni, James Dekker, Giorgio Allegato, Klaus-Dieter Lang

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

3 Citations (Scopus)

Abstract

The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. The packaging of the timing module consists in the integration of an ASIC together with a Quartz-based or Twin-Silicon resonator MEMS which require to be hermetically sealed under vacuum for proper function. The 3D-integration enables a significant miniaturization of the complete system. Subsequently a BAW (Bulk Acoustic Wave) resonator can be further associated over the quartz resonator to form a MEMS-based freely programmable oscillator for stable clock generation, covering a large frequency range between 1 and 50 MHz. The principal fabrication processes include the implementation of Through-Silicon Vias (TSV) in active CMOS wafers, temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and formation of electrical interconnects. The components were packaged by chip to wafer assembly onto active CMOS wafers with TSVs and subsequent wafer to wafer bonding with a corresponding cavity cap wafer for vacuum encapsulation. All processes have been developed and performed at 200 mm industrial wafer scale.
Original languageEnglish
Title of host publicationDesign, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on
PublisherIEEE Institute of Electrical and Electronic Engineers
Pages1-6
ISBN (Electronic)978-1-5090-1457-6, 978-1-5090-1458-3
ISBN (Print)978-1-5090-1391-3
DOIs
Publication statusPublished - 18 Jul 2016
MoE publication typeA4 Article in a conference publication
Event18th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2016 - Budapest, Hungary
Duration: 30 May 20162 Jun 2016
Conference number: 18

Conference

Conference18th Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS, DTIP 2016
Abbreviated titleDTIP 2016
CountryHungary
CityBudapest
Period30/05/162/06/16

Keywords

  • ASIC
  • Au/Sn
  • bonding
  • CMOS
  • encapsulation
  • interposer
  • MEMS resonator
  • Packaging
  • sealing
  • TSV
  • vacuum
  • via last
  • wafer
  • WLP

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  • Cite this

    Manier, C-A., Zoschke, K., Wilke, M., Oppermann, H., Ruffieux, D., Dalla Piazza, S., Suni, T., Dekker, J., Allegato, G., & Lang, K-D. (2016). Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems. In Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 2016 Symposium on (pp. 1-6). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/DTIP.2016.7514832