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Wafer-scale graphene Josephson field-effect transistors and device models for superconducting integrated circuits

  • Aalto University

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

Abstract

The superconducting transistor, or Josephson Field Effect Transistor (JoFET), is a versatile building block for ultra-low-power and high-energy-efficiency classical and quantum electronics. In a JoFET, the superconducting (zero-resistance) current is controlled by electrostatic gate voltage, which enables the scalability of solid-state quantum computers and the creation of next-generation superconducting integrated circuits (ICs). The development of JoFETs has so far been limited to single devices or a few-transistor circuits due to the lack of reproducible technological platform. Here, we report on technological progress of wafer-scale JoFET fabrication, achieving a 98% yield on a 150 mm wafer platform. Now that the large-scale and reproducible fabrication JoFETs has become feasible, we present behavioral and physics models as the required steps toward the design of novel JoFET-based ICs. Using the presented models, we obtain a good description of experimental data, thus paving the way for the design of next-generation superconducting ICs.

Original languageEnglish
Title of host publication7th IEEE International Conference on Emerging Electronics, ICEE 2025
PublisherIEEE Institute of Electrical and Electronic Engineers
ISBN (Electronic)979-8-3315-5547-4
DOIs
Publication statusPublished - 2025
MoE publication typeA4 Article in a conference publication
Event7th IEEE International Conference on Emerging Electronics, ICEE 2025 - Bengaluru, India
Duration: 13 Dec 202516 Dec 2025

Conference

Conference7th IEEE International Conference on Emerging Electronics, ICEE 2025
Country/TerritoryIndia
CityBengaluru
Period13/12/2516/12/25

Funding

This research has been financially supported by Research Council of Finland (projects no. 362345, 362348 and 350325).

Keywords

  • circuit-level design
  • CMOS-compatible processing
  • CVD graphene
  • device model
  • energy-efficiency
  • Josephson junction field-effect transistor (JoFET)
  • Superconducting integrated circuits
  • wafer-scale

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