Abstract
The superconducting transistor, or Josephson Field Effect Transistor (JoFET), is a versatile building block for ultra-low-power and high-energy-efficiency classical and quantum electronics. In a JoFET, the superconducting (zero-resistance) current is controlled by electrostatic gate voltage, which enables the scalability of solid-state quantum computers and the creation of next-generation superconducting integrated circuits (ICs). The development of JoFETs has so far been limited to single devices or a few-transistor circuits due to the lack of reproducible technological platform. Here, we report on technological progress of wafer-scale JoFET fabrication, achieving a 98% yield on a 150 mm wafer platform. Now that the large-scale and reproducible fabrication JoFETs has become feasible, we present behavioral and physics models as the required steps toward the design of novel JoFET-based ICs. Using the presented models, we obtain a good description of experimental data, thus paving the way for the design of next-generation superconducting ICs.
| Original language | English |
|---|---|
| Title of host publication | 7th IEEE International Conference on Emerging Electronics, ICEE 2025 |
| Publisher | IEEE Institute of Electrical and Electronic Engineers |
| ISBN (Electronic) | 979-8-3315-5547-4 |
| DOIs | |
| Publication status | Published - 2025 |
| MoE publication type | A4 Article in a conference publication |
| Event | 7th IEEE International Conference on Emerging Electronics, ICEE 2025 - Bengaluru, India Duration: 13 Dec 2025 → 16 Dec 2025 |
Conference
| Conference | 7th IEEE International Conference on Emerging Electronics, ICEE 2025 |
|---|---|
| Country/Territory | India |
| City | Bengaluru |
| Period | 13/12/25 → 16/12/25 |
Funding
This research has been financially supported by Research Council of Finland (projects no. 362345, 362348 and 350325).
Keywords
- circuit-level design
- CMOS-compatible processing
- CVD graphene
- device model
- energy-efficiency
- Josephson junction field-effect transistor (JoFET)
- Superconducting integrated circuits
- wafer-scale
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JOLI: 2D Josephson FET Low Power Integrated Circuits
Generalov, A. (PI) & Bohuslavskyi, H. (Participant)
13/06/24 → 31/12/28
Project: Research Council of Finland
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CRYOPROC: Cryogenic silicon neuromorphic processor for quantum computing
Bohuslavskyi, H. (Manager)
1/09/22 → 31/08/25
Project: Research Council of Finland
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