Abstract
Silicon photonics is arguably the most promising platform for the demonstration and commercialization of various next generation photonic technologies, thanks to its massive scalability and co-packaging with advanced CMOS electronics. To deliver its full promise, an ultra-low-loss waveguide platform with advanced 3D integration capabilities is crucial. VTT’s 3 µm SOI platform offers record low propagation loss (2.7 dB/m) and insertion loss, with negligible polarization sensitivity. However, due to its bigger core, monolithic integration of active components by evanescent coupling is challenging. Here we solve the problem with a waveguide escalator technology that lifts the fundamental mode from the SOI core layer to the aSi:H upper layer where active devices such as, electro-optic modulator or superconducting nanowire singe photon detectors (SNSPD) will be integrated. Due to its thicker topology, some special design and fabrication techniques are adopted, which will be presented along with the experimental demonstration of the escalator.
| Original language | English |
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| DOIs | |
| Publication status | Published - 20 Mar 2025 |
| MoE publication type | Not Eligible |
| Event | Silicon Photonics XX 2025 - San Francisco, United States Duration: 28 Jan 2025 → 30 Jan 2025 |
Conference
| Conference | Silicon Photonics XX 2025 |
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| Country/Territory | United States |
| City | San Francisco |
| Period | 28/01/25 → 30/01/25 |
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